64Mb: x32
SDRAM
TRUTH TABLE 3 – CURRENT STATE BANK n, COMMAND TO BANK n
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS# RAS# CAS# WE#
COMMAND (ACTION)
NOTES
Any
Idle
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
L
AUTO REFRESH
7
7
L
L
LOAD MODE REGISTER
L
H
L
L
PRECHARGE
11
10
10
8
H
H
L
H
L
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
Row Active
L
H
L
L
Read
(Auto
H
H
L
H
L
10
10
8
L
Precharge
Disabled)
Write
H
H
L
L
H
H
H
L
L
9
H
L
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
10
10
8
(Auto
L
Precharge
Disabled)
H
H
L
H
L
9
NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the
commands shown are those allowed to be issued to that bank when in that state. Exceptions are
covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND
INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock
edge occurring during these states. Allowable commands to the other bank are determined by its
current state and Truth Table 3, and according to Truth Table 4.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met.
Once tRP is met, the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once
tRCD is met, the bank will be in the row active state.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and
t
t
ends when RP has been met. Once RP is met, the bank will be in the idle state.
64Mb: x32 SDRAM
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
26
©2002,MicronTechnology,Inc.
MICRON [ MICRON TECHNOLOGY ]
