64Mb: x32 SDRAM
Mode Register
CAS Latency
The CAS latency (CL) is the delay, in clock cycles, between the registration of a READ
command and the availability of the output data. The latency can be set to two or three
clocks.
If a READ command is registered at clock edge
n,
and the latency is
m
clocks, the data
will be available by clock edge
n + m.
The DQ start driving as a result of the clock edge
one cycle earlier (n
+ m
- 1), and provided that the relevant access times are met, the
data is valid by clock edge
n + m.
For example, assuming that the clock cycle time is
such that all relevant access times are met, if a READ command is registered at T0 and
the latency is programmed to two clocks, the DQ start driving after T1 and the data is
valid by T2.
Reserved states should not be used as unknown operation or incompatibility with fu-
ture versions may result.
Figure 14: CAS Latency
T0
CLK
Command
READ
NOP
tLZ
DQ
tAC
CL = 2
T0
CLK
Command
READ
NOP
NOP
tLZ
DQ
CL = 3
tAC
NOP
tOH
D
OUT
T1
T2
T3
T4
NOP
tOH
D
OUT
T1
T2
T3
Don’t Care
Undefined
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use. Reserved states should not
be used because unknown operation or incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M[2:0] applies to both READ and
WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
PDF: 09005aef811ce1fe
64mb_x32_sdram.pdf - Rev. T 04/13 EN
42
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