64Mb: x32 SDRAM
Functional Description
Functional Description
In general, this 64Mb SDRAM device (512K x 32x 4 banks) is a quad-bank DRAM that
operates at 3.3V and include a synchronous interface. All signals are registered on the
positive edge of the clock signal, CLK. Each of the 16,777,216-bit banks is organized as
2048 rows by 256 columns by 32 bits.
Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an ACTIVE command, followed by a
READ or WRITE command. The address bits registered coincident with the ACTIVE
command are used to select the bank and row to be accessed (BA0 and BA1 select the
bank, A[10:0] select the row). The address bits (A[7:0]) registered coincident with the
READ or WRITE command are used to select the starting column location for the burst
access.
Prior to normal operation, the device must be initialized. The following sections provide
detailed information covering device initialization, register definition, command de-
scriptions, and device operation.
PDF: 09005aef811ce1fe
64mb_x32_sdram.pdf - Rev. T 04/13 EN
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