512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Fu n ct io n a l Blo ck Dia g ra m s
The 512Mb SDRAM is designed to operate in 1.8V low-power memory systems. An auto
refresh mode is provided, along with a power-saving deep power-down mode. All inputs
and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks in order to hide precharge
time, and the capability to randomly change column addresses on each clock cycle
during a burst access.
Fu n ct io n a l Blo ck Dia g ra m s
Fig u re 2:
32 Me g x 16 SDRAM
BA1
BA0
Bank
0
0
1
1
0
1
0
1
0
1
2
3
CKE
CLK
CONTROL
LOGIC
CS#
WE#
BANK3
CAS#
RAS#
BANK2
BANK1
EXT MODE
REGISTER
REFRESH
13
COUNTER
MODE REGISTER
BANK0
ROW-
ADDRESS
LATCH
AND
DECODER
ROW-
ADDRESS
MUX
13
BANK0
MEMORY
ARRAY
2
2
13
8,192
DQML,
DQMH
13
(8,192 x 1,024 x 16)
DATA
OUTPUT
REGISTER
SENSE AMPLIFIERS
16,384
16
DQ0–
DQ15
I/O GATING
2
16
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
BANK
CONTROL
LOGIC
A0–A12,
BA0, BA1
ADDRESS
REGISTER
15
DATA
INPUT
REGISTER
2
16
1,024
(x16)
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
10
10
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
6
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