512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
No t e s
Ta b le 16:
Pa ra m e t e r
Ca p a cit a n ce (x16)
Note: 2; notes appear on pages 51–52
Sym b o l
Min
Ma x
Un it s
CI1
CI2
CIO
2.0
2.0
2.5
5.0
5.0
6.0
pF
pF
pF
Input capacitance: CLK
Input capacitance: All other input-only balls
Input/Output capacitance: DQs
Ta b le 17:
Pa ra m e t e r
Ca p a cit a n ce (x32)
Note: 2; notes appear on pages 51–52
Sym b o l
Min
Ma x
Un it s
CI1
CI2
CIO
2.0
2.0
2.5
5.0
5.0
6.0
pF
pF
pF
Input capacitance: CLK
Input capacitance: All other input-only balls
Input/Output capacitance: DQs
No t e s
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD, VDDQ = +1.8V; T = 25°C; ball under test biased at
A
0.9V, 1.25V, and 1.4V, respectively; f = 1 MHz.
3. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range (–40°C ≤ T ≤ +85°C for T on IT parts) is
A
A
ensured.
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be pow-
ered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO
t
REFRESH command wake-ups should be repeated any time the REF refresh require-
ment is exceeded.
7. AC characteristics assume T = 1ns.
t
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
sit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured for 1.8V at 0.9V with equivalent load:
Q
20pF
Test loads with full DQ driver strength. Performance will vary with actual system DQ
bus capacitive loading, termination, and programmed drive strength.
t
10. HZ defines the time at which the output achieves the open circuit condition; it is not
t
a reference to VOH or VOL. The last valid data element will meet OH before going
High-Z.
11. AC timing and IDD tests have VIL and VIH, with timing referenced to VIH/ 2 = crossover
t
point. If the input transition time is longer than T (MAX), then the timing is refer-
enced at VIL (MAX) and VIH (MIN) and no longer at the VIH/ 2 crossover point.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
51
©2005 Micron Technology, Inc. All rights reserved.
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