1Gb: x4, x8, x16 DDR3 SDRAM
Mode Register 0 (MR0)
ing location within the block. The programmed burst length applies to both READ and
WRITE bursts.
Figure 53: Mode Register 0 (MR0) Definitions
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
16 15 14 13 12 11 10
9
8
7
1
6
5
4
3
2
1
0
Mode register 0 (MR0)
1
1
0
0
PD
WR
DLL
0
CAS# latency BT CL
0
0
M1 M0
Burst Length
M15 M14
Mode Register
0
0
1
1
0
1
0
1
Fixed BL8
4 or 8 (on-the-fly via A12)
Fixed BC4 (chop)
Reserved
0
0
1
1
0
1
0
1
Mode register 0 (MR0)
Mode register 1 (MR1)
Mode register 2 (MR2)
Mode register 3 (MR3)
M8 DLL Reset
M12 Precharge PD
0
1
No
0
1
DLL off (slow exit)
DLL on (fast exit)
Yes
M11 M10 M9 Write Recovery
M6 M5 M4 M2
CAS Latency
M3
READ Burst Type
Sequential (nibble)
Interleaved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16
5
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
Reserved
0
1
5
6
6
7
7
8
8
10
12
14
9
10
11
12
13
14
1. MR0[16, 13, 7, 2] are reserved for future use and must be programmed to 0.
Note:
Burst Type
Accesses within a given burst may be programmed to either a sequential or an inter-
leaved order. The burst type is selected via MR±[3] (see Figure 53 (page 138)). The order-
ing of accesses within a burst is determined by the burst length, the burst type, and the
starting column address. DDR3 only supports 4-bit burst chop and 8-bit burst access
modes. Full interleave address ordering is supported for READs, while WRITEs are re-
stricted to nibble (BC4) or word (BL8) boundaries.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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138
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