256Mb, 3V Multiple I/O Serial Flash Memory
ONE-TIME PROGRAMMABLE Operations
The write enable latch bit is cleared to 0, whether the operation is successful or not, and
the status register and flag status register can be polled for the operation status. When
the operation completes, the write in progress bit is cleared to 0.
If the operation times out, the write enable latch bit is reset and the program fail bit is
set to 1. If S# is not driven HIGH, the command is not executed, flag status register error
bits are not set, and the write enable latch remains set to 1. The operation is considered
complete once bit 7 of the flag status register outputs 1 with at least one byte output.
The OTP control byte (byte 64) is used to permanently lock the OTP memory array.
Table 32: OTP Control Byte (Byte 64)
Bit Name
OTP control byte
Settings
Description
0
0 = Locked
1 = Unlocked (default)
Used to permanently lock the 64-byte OTP array. When bit 0 = 1,
the 64-byte OTP array can be programmed. When bit 0 = 0, the
64-byte OTP array is read only.
Once bit 0 has been programmed to 0, it can no longer be
changed to 1. Program OTP array is ignored, the write enable
latch bit remains set, and flag status register bits 1 and 4 are set.
Figure 44: PROGRAM OTP Command Timing
Extended
0
7
8
C
x
C
LSB
A[MIN]
LSB
D
D
D
D
D
D
D
D
D
IN
DQ0
Command
IN
IN
IN
IN
IN
IN
IN
IN
MSB
A[MAX]
MSB
Dual
0
3
4
C
x
C
LSB
A[MIN]
LSB
D
D
D
D
D
IN
DQ[1:0]
Command
IN
IN
IN
IN
MSB
A[MAX]
MSB
Quad
0
1
2
C
x
C
LSB
A[MIN]
LSB
D
D
D
IN
DQ[3:0]
Command
IN
IN
MSB
A[MAX]
MSB
1. For extended-SPI protocol, Cx = 7 + (A[MAX] + 1); For dual-SPI protocol, Cx = 3 + (A[MAX]
+ 1)/2; For quad-SPI protocol, Cx = 1 + (A[MAX] + 1)/4.
Note:
CCMTD-1725822587-3368
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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