欢迎访问ic37.com |
会员登录 免费注册
发布采购

MT250QL01GABA3EW70AITES 参数 Datasheet PDF下载

MT250QL01GABA3EW70AITES图片预览
型号: MT250QL01GABA3EW70AITES
PDF下载: 下载PDF文件 查看货源
内容描述: [3V, Multiple I/O, 4KB, 32KB, 64KB, Sector Erase]
分类和应用:
文件页数/大小: 97 页 / 1038 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号MT250QL01GABA3EW70AITES的Datasheet PDF文件第1页浏览型号MT250QL01GABA3EW70AITES的Datasheet PDF文件第2页浏览型号MT250QL01GABA3EW70AITES的Datasheet PDF文件第3页浏览型号MT250QL01GABA3EW70AITES的Datasheet PDF文件第4页浏览型号MT250QL01GABA3EW70AITES的Datasheet PDF文件第6页浏览型号MT250QL01GABA3EW70AITES的Datasheet PDF文件第7页浏览型号MT250QL01GABA3EW70AITES的Datasheet PDF文件第8页浏览型号MT250QL01GABA3EW70AITES的Datasheet PDF文件第9页  
256Mb, 3V Multiple I/O Serial Flash Memory  
Features  
List of Figures  
Figure 1: Part Number Ordering Information .................................................................................................... 2  
Figure 2: Block Diagram .................................................................................................................................. 9  
Figure 3: Logic Diagram ................................................................................................................................. 10  
Figure 4: 24-Ball T-BGA, 5 x 5 (Balls Down) ..................................................................................................... 11  
Figure 5: 24-Ball TBGA, 4 x 6 (Balls Down) ...................................................................................................... 12  
Figure 6: 16-Pin, Plastic Small Outline – SO16 (Top View) ................................................................................ 13  
Figure 7: 8-Pin, SOP2 or W-PDFN (Top View) ................................................................................................. 14  
Figure 8: 24-Ball T-PBGA (5 x 5 ball grid array) – 6mm x 8mm .......................................................................... 17  
Figure 9: 24-Ball T-PBGA (24b05) – 6mm x 8mm ............................................................................................. 18  
Figure 10: 16-Pin SOP2 – 300 Mils Body Width ................................................................................................ 19  
Figure 11: W-PDFN-8 (MLP8) – 6mm x 5mm .................................................................................................. 20  
Figure 12: W-PDFN-8 (MLP8) – 8mm x 6mm .................................................................................................. 21  
Figure 13: Memory Array Segments ................................................................................................................ 26  
Figure 14: Internal Configuration Register ...................................................................................................... 27  
Figure 15: Sector and Password Protection ..................................................................................................... 34  
Figure 16: RESET ENABLE and RESET MEMORY Command ........................................................................... 45  
Figure 17: READ ID and MULTIPLE I/O READ ID Commands ......................................................................... 46  
Figure 18: READ SERIAL FLASH DISCOVERY PARAMETER Command – 5Ah ................................................... 47  
Figure 19: READ – 03h/13h3 ........................................................................................................................... 50  
Figure 20: FAST READ – 0Bh/0Ch3 ................................................................................................................. 50  
Figure 21: DUAL OUTPUT FAST READ – 3Bh/3Ch3 ......................................................................................... 51  
Figure 22: DUAL INPUT/OUTPUT FAST READ – BBh/BCh3 ............................................................................ 51  
Figure 23: QUAD OUTPUT FAST READ – 6Bh/6Ch3 ........................................................................................ 52  
Figure 24: QUAD INPUT/OUTPUT FAST READ – EBh/ECh3 ............................................................................ 52  
Figure 25: QUAD INPUT/OUTPUT WORD READ – E7h3 ................................................................................. 53  
Figure 26: DTR FAST READ – 0Dh/0Eh3 .......................................................................................................... 54  
Figure 27: DTR DUAL OUTPUT FAST READ – 3Dh3 ........................................................................................ 54  
Figure 28: DTR DUAL INPUT/OUTPUT FAST READ – BDh3 ............................................................................ 55  
Figure 29: DTR QUAD OUTPUT FAST READ – 6Dh3 ........................................................................................ 56  
Figure 30: DTR QUAD INPUT/OUTPUT FAST READ – EDh3 ............................................................................ 56  
Figure 31: WRITE ENABLE and WRITE DISABLE Timing ................................................................................. 57  
Figure 32: READ REGISTER Timing ................................................................................................................ 58  
Figure 33: WRITE REGISTER Timing .............................................................................................................. 60  
Figure 34: CLEAR FLAG STATUS REGISTER Timing ........................................................................................ 61  
Figure 35: PAGE PROGRAM Command .......................................................................................................... 63  
Figure 36: DUAL INPUT FAST PROGRAM Command ...................................................................................... 64  
Figure 37: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 64  
Figure 38: QUAD INPUT FAST PROGRAM Command ..................................................................................... 65  
Figure 39: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 65  
Figure 40: SUBSECTOR and SECTOR ERASE Timing ....................................................................................... 67  
Figure 41: BULK ERASE Timing ...................................................................................................................... 67  
Figure 42: PROGRAM/ERASE SUSPEND and RESUME Timing ........................................................................ 69  
Figure 43: READ OTP ARRAY Command Timing ............................................................................................. 70  
Figure 44: PROGRAM OTP Command Timing ................................................................................................. 71  
Figure 45: ENTER DEEP POWER-DOWN Timing ............................................................................................. 73  
Figure 46: RELEASE FROM DEEP POWER-DOWN Timing ............................................................................... 74  
Figure 47: XIP Mode Directly After Power-On .................................................................................................. 79  
Figure 48: Power-Up Timing .......................................................................................................................... 82  
Figure 49: AC Timing Input/Output Reference Levels ...................................................................................... 86  
Figure 50: Reset AC Timing During PROGRAM and ERASE Cycle ..................................................................... 92  
CCMTD-1725822587-3368  
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
© 2014 Micron Technology, Inc. All rights reserved.  
5
 复制成功!