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MT250QL01GABA3EW70AITES 参数 Datasheet PDF下载

MT250QL01GABA3EW70AITES图片预览
型号: MT250QL01GABA3EW70AITES
PDF下载: 下载PDF文件 查看货源
内容描述: [3V, Multiple I/O, 4KB, 32KB, 64KB, Sector Erase]
分类和应用:
文件页数/大小: 97 页 / 1038 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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256Mb, 3V Multiple I/O Serial Flash Memory  
Status Register  
Status Register  
Status register bits can be read from or written to using READ STATUS REGISTER or  
WRITE STATUS REGISTER commands, respectively. When the status register enable/  
disable bit (bit 7) is set to 1 and W# is driven LOW, the status register nonvolatile bits  
become read-only and the WRITE STATUS REGISTER operation will not execute. The  
only way to exit this hardware-protected mode is to drive W# HIGH.  
Table 3: Status Register  
Bit  
Name  
Settings  
Description  
Notes  
7
Status register  
write enable/disa-  
ble  
0 = Enabled (Default)  
1 = Disabled  
Nonvolatile control bit: Used with W# to enable or  
disable writing to the status register.  
5
Top/bottom  
0 = Top (Default)  
1 = Bottom  
Nonvolatile control bit: Determines whether the pro-  
tected memory area defined by the block protect bits  
starts from the top or bottom of the memory array.  
6, 4:2 BP[3:0]  
See Protected Area ta-  
bles  
Nonvolatile control bit: Defines memory to be soft-  
ware protected against PROGRAM or ERASE operations.  
When one or more block protect bits is set to 1, a desig-  
nated memory area is protected from PROGRAM and  
ERASE operations.  
1
1
0
Write enable latch 0 = Clear (Default)  
1 = Set  
Volatile control bit: The device always powers up with  
this bit cleared to prevent inadvertent WRITE, PRO-  
GRAM, or ERASE operations. To enable these operations,  
the WRITE ENABLE operation must be executed first to  
set this bit.  
Write in progress  
0 = Ready (Default)  
1 = Busy  
Volatile status bit: Indicates if one of the following  
command cycles is in progress:  
WRITE STATUS REGISTER  
2
WRITE NONVOLATILE CONFIGURATION REGISTER  
PROGRAM  
ERASE  
1. The BULK ERASE command is executed only if all bits = 0.  
2. Status register bit 0 is the inverse of flag status register bit 7.  
Notes:  
CCMTD-1725822587-3368  
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
© 2014 Micron Technology, Inc. All rights reserved.  
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