256MB, 512MB, 1GB (x72, ECC, DR), PC3200
184-PIN DDR SDRAM UDIMM
Fig u re 5: CAS La t e n cy Dia g ra m
Ta b le 6:
Bu rst De fin it io n Ta b le
T0
T1
T2
T2n
T3
T3n
STARTING
COLUMN
ADDRESS
CK#
CK
BURST
LENGTH
ORDER OF ACCESSES WITHIN
A BURST
COMMAND
READ
NOP
NOP
NOP
TYPE =
TYPE =
SEQUENTIAL INTERLEAVED
CL = 3
A0
0
1
DQS
DQ
2
4
0-1
1-0
0-1
1-0
A1 A0
0
0
1
1
0
1
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
T0
T1
T2
T2n
T3
T3n
CK#
CK
COMMAND
READ
NOP
NOP
NOP
A2 A1 A0
CL = 2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
DQS
DQ
8
T0
T1
T2
T2n
T3
T3n
CK#
CK
COMMAND
READ
NOP
NOP
NOP
CL = 2.5
NOTE:
DQS
DQ
1. For a burst length of two, A1-Ai select the two-data-ele-
ment block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai select the four-data-
element block; A0-A1 select the first access within the
block.
Burst Length = 4 in the cases shown
Shown with nominal AC, DQSCK, and DQSQ
t
t
t
3. For a burst length of eight, A3-Ai select the eight-data-
element block; A0-A2 select the first access within the
block.
TRANSITIONING DATA DON’T CARE
4. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
Op e ra t in g Mo d e
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7–A11 (for
256MB), or A7–A12 (512MB, 1GB) each set to zero, and
bits A0–A6 set to the desired values. A DLL reset is ini-
tiated by issuing a MODE REGISTER SET command
with bits A7 and A9–A11 (256MB), or A7 and A9–A12
(512MB, 1GB) each set to zero, bit A8 set to one, and
bits A0–A6 set to the desired values. Although not
required by the Micron device, JEDEC specifications
recommend when a LOAD MODE REGISTER com-
m and is issued to reset the DLL, it should always be
followed by a LOAD MODE REGISTER com m and to
select normal operating mode.
5. i = 9 (256MB, 512MB);
i = 9, 11 (1GB)
Ta b le 7:
CAS La t e n cy (CL) Ta b le
ALLOWABLE OPERATING
FREQUENCY (MHZ)
SPEED
CL = 2
CL = 2.5
CL = 3
-40B
75 ≤ f ≤ 133 75 ≤ f ≤ 167 125 ≤ f ≤ 200
All other combinations of values for A7–A11
(256MB), or A7–A12 (512MB, 1GB) are reserved for
future use and/ or test modes. Test modes and
pdf: 09005aef80814e61, source: 09005aef80a43eed
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
9
MICRON [ MICRON TECHNOLOGY ]
