256MB, 512MB, 1GB (x72, ECC, DR), PC3200
184-PIN DDR SDRAM UDIMM
reserved states should not be used because unknown
operation or incompatibility with future versions may
result.
Fig u re 6: Ext e n d e d Mo d e Re g ist e r
De fin it io n Dia g ra m
256MB Module
Ext e n d e d Mo d e Re g ist e r
BA0
A8
A9
A6 A5 A4
A1
A0
Address Bus
BA1
A10
A7
A3 A2
A11
The extended m ode register controls functions
beyond those controlled by the mode register; these
additional functions are DLL enable/ disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 6, Extended Mode Register
Definition Diagram, on page 10. The extended mode
register is programmed via the LOAD MODE REGIS-
TER command to the mode register (with BA0 = 1 and
BA1 = 0) and will retain the stored information until it
is program m ed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/ BA1 both LOW) to reset the DLL.
13 12 11 10
9
8
7
6
5
4
3
2
1
0
Extended Mode
Register (Ex)
1
1
0
1
Operating Mode
DS DLL
512MB, 1GB Modules
A8
A9
A6 A5 A4
A1
A0
Address Bus
BA1
A10
A7
A3 A2
BA0 A12 A11
14 13 12 11 10
01 11
9
8
7
6
5
4
3
2
1
0
Extended Mode
Register (Ex)
Operating Mode
DS DLL
The extended mode register m ust be loaded when
all device banks are idle and no bursts are in progress,
and the controller m ust wait the specified tim e before
initiating any subsequent operation. Violating either
of these requirements could result in unspecified oper-
ation.
DLL
E0
0
1
Enable
Disable
E12 E11 E10 E9 E8 E7 E6
E4 E3 E22
E1, E0
Operating Mode
Reserved
E5
0
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
Valid
–
DLL En a b le /Disa b le
–
Reserved
The DLL m ust be enabled for normal operation.
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled autom atically.) Any tim e the DLL is enabled,
200 clock cycles must occur before a READ command
can be issued.
NOTE:
1. E13 and E12 (256MB), or E14 and E13 (512MB, 1GB)
(BA1 and BA0) must be “0, 1” to select the Extended
Mode Register (vs. the base Mode Register).
2. The QFC# option is not supported.
pdf: 09005aef80814e61, source: 09005aef80a43eed
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
10
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