256MB, 512MB, 1GB (x72, ECC, DR), PC3200
184-PIN DDR SDRAM UDIMM
Bu rst Le n g t h
Fig u re 4: Mo d e Re g ist e r De fin it io n
Read and write accesses to the DDR SDRAM are
burst oriented, with the burst length being program-
mable, as shown in Figure 4, Mode Register Definition
Diagram . The burst length determ ines the m aximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and
the interleaved burst types.
Dia g ra m
256MB Module
BA1
A8
A9
A6 A5 A4
A1
A0
Address Bus
BA0
A10
A7
A3 A2
A11
13 12 11 10
9
8
7
6
5
4
3
2
1
0
Mode Register (Mx)
0* 0*
Operating Mode
CAS Latency BT Burst Length
* M13 and M12 (BA1and BA0)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, m eaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1–Ai when the burst length is set to two,
by A2–Ai when the burst length is set to four and by
A3–Ai when the burst length is set to eight (where Ai is
the most significant column address bit for a given
configuration; see Note 5 of Table 6, Burst Definition
Table, on page 9). The remaining (least significant)
address bit(s) is (are) used to select the starting loca-
tion within the block. The programmed burst length
applies to both READ and WRITE bursts.
512MB, 1GB Modules
BA1
A8
A9
A6 A5 A4
A1
A0
Address Bus
BA0
A10
A7
A3 A2
A12 A11
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Mode Register (Mx)
0* 0*
Operating Mode
CAS Latency BT Burst Length
* M14 and M13 (BA1 and BA0)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
Burst Length
M2 M1 M0
M3 = 0
Reserved
2
M3 = 1
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4
4
8
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bu rst Typ e
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
m ined by the burst length, the burst type and the start-
ing column address, as shown in Table 6, Burst
Definition Table, on page 9.
Burst Type
Sequential
Interleaved
M3
0
1
CAS Latency
Reserved
Reserved
2
M6 M5 M4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Re a d La t e n cy
3
The READ latency is the delay, in clock cycles,
between the registration of a READ com m and and the
availability of the first bit of output data. The latency
can be set to 3, 2.5, or 2 clocks, as shown in Figure 5,
CAS Latency Diagram, on page 9.
Reserved
Reserved
2.5
Reserved
If a READ com m and is registered at clock edge n,
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 7,
CAS Latency (CL) Table, on page 9, indicates the oper-
ating frequencies at which each CAS latency setting
can be used.
M12 M11 M10 M9 M8 M7
M6-M0
Valid
Valid
-
Operating Mode
Normal Operation
0
0
-
0
0
-
0
0
-
0
0
-
0
1
-
0
0
-
Normal Operation/Reset DLL
All other states reserved
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
pdf: 09005aef80814e61, source: 09005aef80a43eed
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
8
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