256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
Mode register bits A0–A2 specify the burst length,
A3 specifies the type of burst (sequential or inter-
leaved), A4–A6 specify the CAS latency, and A7–A11
(256MB) or A7–A12 (512MB, 1GB), or A7–A13 (2GB)
specify the operating mode.
Fig u re 5: Mo d e Re g ist e r De fin it io n
Dia g ra m
256MB Module
BA1
A8
A9
A6 A5 A4
A1
A0
Address Bus
BA0
A10
A7
A3 A2
A11
Bu rst Typ e
13
11
9
8
6
5
4
1
12
10
7
3
2
0
Mode Register (Mx)
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
m ined by the burst length, the burst type and the start-
ing column address, as shown in Table 6, Burst
Definition Table, on page 10.
0* 0*
Operating Mode
CAS Latency BT Burst Length
* M13 and M12 (BA0 and BA1) must be “0, 0” to select the
base mode register (vs. the extended mode register).
512MB and 1GB Modules
BA1
A8
A9
A6 A5 A4
A1
A0
Address Bus
BA0
A10
A7
A3 A2
A12 A11
14 13
11
9
8
6
5
4
1
12
10
7
3
2
0
Mode Register (Mx)
0* 0*
Operating Mode
CAS Latency BT Burst Length
Bu rst Le n g t h
* M14 and M13 (BA0 and BA1) must be “0, 0” to select the
base mode register (vs. the extended mode register).
Read and write accesses to the DDR SDRAM are
burst oriented, with the burst length being program-
mable, as shown in Figure 5, Mode Register Definition
Diagram . The burst length determ ines the m aximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and
the interleaved burst types.
2GB Module
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Mode Register (Mx)
0* 0*
Operating Mode
CAS Latency BT Burst Length
* M15 and M14 (BA1 and BA0)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
Burst Length
M2 M1 M0
M3 = 0
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, m eaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1–Ai when the burst length is set to two,
by A2-Ai when the burst length is set to four and by A3-
Ai when the burst length is set to eight (where Ai is the
most significant column address bit for a given config-
uration; see Note 5, of Table 6, Burst Definition Table,
on page 10). The remaining (least significant) address
bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to
both READ and WRITE bursts.
4
8
Reserved
Reserved
Reserved
Reserved
Burst Type
Sequential
Interleaved
M3
0
1
CAS Latency
Reserved
Reserved
2
M6 M5 M4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
2.5
Re a d La t e n cy
The READ latency is the delay, in clock cycles,
between the registration of a READ com m and and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 6, CAS
Latency Diagram.
Reserved
M13 M12 M11 M10 M9 M8 M7
M6-M0
Valid
Valid
-
Operating Mode
0
0
-
0
0
-
0
0
-
0
0
-
0
0
-
0
1
-
0
0
-
Normal Operation
Normal Operation/Reset DLL
All other states reserved
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
9
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