256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
Ta b le 18: EEPROM De vice Se le ct Co d e
The most significant bit (b7) is sent first
DEVICE TYPE IDENTIFIER
CHIP ENABLE
b 2
RW
b 0
SELECT CODE
b 7
b 6
b 5
b 4
b 3
b 1
Memory Area Select Code (two arrays)
Protection Register Select Code
1
0
0
1
1
1
0
0
SA2
SA2
SA1
SA1
SA0
SA0
RW
RW
Ta b le 19: EEPROM Op e ra t in g Mo d e s
MODE
RW BIT
WC
BYTES INITIAL SEQUENCE
1
0
1
1
0
0
VIH or VIL
VIH or VIL
VIH or VIL
VIH or VIL
VIL
1
1
Current Address Read
Random Address Read
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
1
≥ 1
1
Sequential Read
Byte Write
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
VIL
≤ 16
Page Write
START, Device Select, RW = ‘0’
Fig u re 16: SPD EEPROM Tim in g Dia g ra m
t
t
t
F
HIGH
R
t
LOW
SCL
t
t
t
t
t
SU:STO
SU:STA
HD:STA
HD:DAT
SU:DAT
SDA IN
t
t
t
DH
AA
BUF
SDA OUT
UNDEFINED
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
27
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