256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
31. READs and WRITEs with auto precharge are not
allowed to be issued until tRAS (MIN) can be satis-
fied prior to the internal precharge com m and
being issued.
32. Any positive glitch in the nominal voltage must be
less than 1/ 3 of the clock and not more than
+400mV or 2.9V, whichever is less. Any negative
glitch must be less than 1/ 3 of the clock cycle and
not exceed either 300mV or 2.2V, whichever is
more positive. However, the DC average cannot be
below 2.3V minimum.
drain-to-source voltages from 0.1V to 1.0 Volt,
and at the sam e voltage and tem perature.
f. The full variation in the ratio of the nom inal
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
34. The voltage levels used are derived from a mini-
mum VDD level and the referenced test load. In
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
33. Normal Output Drive Curves:
35. VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a
pulse width ≤ 3ns and the pulse width can not be
greater than 1/ 3 of the cycle rate. VIL undershoot:
VIL (MIN) = -1.5V for a pulse width ≤ 3ns and the
pulse width can not be greater than 1/ 3 of the
cycle rate.
a. The full variation in driver pull-down current
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 9,
Pull-Down Characteristics.
b. The variation in driver pull-down current
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 9, Pull-Down Characteristics.
c. The full variation in driver pull-up current
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 10,
Pull-Up Characteristics.
d. The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
10, Pull-Up Characteristics.
36. VDD and VDDQ must track each other.
t
37. tHZ (MAX) takes precedence over DQSCK (MAX)
t
t
+ RPST (MAX) condition. LZ (MIN) will prevail
over tDQSCK (MIN) + tRPRE (MAX) condition.
38. tRPST end point and RPRE begin point are not
t
referenced to a specific voltage level but specify
when the device output is no longer driving
(tRPST), or begins driving (tRPRE).
39. During initialization, VDDQ, VTT, and VREF must
be equal to or less than VDD + 0.3V. Alternatively,
VTT may be 1.35V maximum during power up,
even if VDD/ VDDQ are 0V, provided a minimum of
42Ω of series resistance is used between the VTT
supply and the input pin.
40. For -335, -262, -26A and -265 speed grades, IDD3N
is specified to be 35mA per DDR SDRAM at 100
MHz.
e. The full variation in the ratio of the maximum
to m inim um pull-up and pull-down current
should be between 0.71 and 1.4, for device
Fig u re 9: Pu ll-Do w n Ch a ra ct e rist ics
Fig u re 10: Pu ll-Up Ch a ra ct e rist ics
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
22
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