256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
Ta b le 12: IDD Sp e cifica t io n s a n d Co n d it io n s – 256MB
DDR SDRAM components only
Notes: 1–5, 8, 10, 14, 48; notes appear on pages 20–23; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V
MAX
-26A/
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-Precharge; RC = RC
SYM
-335
-262
-265 UNITS NOTES
IDD0a
t
t
1,024
904
864
mA
20, 42
t
t
(MIN); CK = CK (MIN); DQ, DM and DQS inputs changing once per clock
cyle; Address and control inputs changing once every two clock cycles
IDD1a
OPERATING CURRENT: One device bank; Active -Read Precharge;
1,104
984
984
mA
20, 42
t
t
Burst = 2; tRC = RC (MIN); tCK = CK (MIN); IOUT = 0mA; Address and
control inputs changing once per clock cycle
IDD2Nb
IDD2Fb
48
48
48
mA 21, 28,
44
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks
t
idle; Power-down mode; tCK = CK (MIN); CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = CK
t
720
720
640
mA
45
MIN; CKE = HIGH; Address and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS, and DM
IDD3Pb
IDD3Nb
400
800
400
800
320
720
mA 21, 28,
44
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active;
t
Power-down mode; tCK = CK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
mA
40
t
t
bank; Active-Precharge; tRC = RAS (MAX); tCK = CK (MIN); DQ, DM
andDQS inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
IDD4Ra
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank
active; Address and control inputs chan-ging once per clock cycle; tCK
1,144
1,144
1,064
1,024
1,024
1,024
mA
mA
20, 42
20
t
= CK (MIN); IOUT = 0mA
IDD4Wa
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice
per clock cycle
IDD5b
tREFC = tRFC (MIN)
4,240
80
3,520
80
3,520
80
mA 20, 24,
AUTO REFRESH CURRENT
44
IDD5Ab
tREFC = 15.625µs
SELF REFRESH CURRENT: CKE ≤ 0.2V
mA
IDD6b
IDD7a
48
48
32
mA
mA
9
2,864
2,664
2,624
20, 43
OPERATING CURRENT: Four device bank interleaving READs (BL = 4)
t
t
t
with auto precharge, RC = RC (MIN); tCK = CK (MIN); Address and
control inputs change only during Active READ, or WRITE commands
NOTE:
a: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2p (CKE LOW) mode.
b: Value calculated reflects all module ranks in this operating condition.
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
14
MICRON [ MICRON TECHNOLOGY ]
