256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
Fig u re 6: CAS La t e n cy Dia g ra m
Ta b le 6:
Bu rst De fin it io n Ta b le
T0
T1
T2
T2n
T3
T3n
ORDER OF ACCESSES WITHIN
A BURST
CK#
CK
STARTING
COLUMN
BURST
TYPE =
TYPE =
COMMAND
READ
NOP
NOP
NOP
LENGTH ADDRESS
SEQUENTIAL INTERLEAVED
CL = 2
A0
DQS
DQ
2
4
0
1
0-1
1-0
0-1
1-0
A1 A0
T0
T1
T2
T2n
T3
T3n
0
0
1
1
0
1
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
CK#
CK
COMMAND
READ
NOP
NOP
NOP
CL = 2.5
A2 A1 A0
DQS
DQ
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
8
Burst Length = 4 in the cases shown
Shown with nominal AC, DQSCK, and DQSQ
t
t
t
TRANSITIONING DATA DON’T CARE
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Figure 7,
CAS Latency (CL) Table, indicates the operating fre-
quencies at which each CAS latency setting can be
used.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
NOTE:
1. For a burst length of two, A1–Ai select the two-data-
element block; A0 selects the first access within the
block.
2. For a burst length of four, A2–Ai select the four-data-
element block; A0–A1 select the first access within the
block.
3. For a burst length of eight, A3–Ai select the eight-data-
element block; A0–A2 select the first access within the
block.
4. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
Op e ra t in g Mo d e
The normal operating mode is selected by issuing a
MODE REGISTER SET com m and with bits A7–A11
(256MB), A7–A12 (512MB, 1GB), or A7–A13 (2GB) each
set to zero, and bits A0–A6 set to the desired values. A
DLL reset is initiated by issuing a MODE REGISTER
SET command with bits A7 and A9–A11 (256MB), A7
and A9–A12 (512MB, 1GB), or A7 and A9–A13
(2GB)each set to zero, bit A8 set to one, and bits A0–A6
set to the desired values. Although not required by the
Micron device, JEDEC specifications recommend
when a LOAD MODE REGISTER command is issued to
reset the DLL, it should always be followed by a LOAD
MODE REGISTER com m and to select norm al operat-
ing mode.
5. i = 9 for 256MB, 512MB;
i = 9, 11 for 1GB, 2GB.
Ta b le 7:
CAS La t e n cy (CL) Ta b le
ALLOWABLE OPERATING
CLOCK FREQUENCY (MHZ)
SPEED
CL = 2
CL = 2.5
-335
-262
-26A
-265
75 ≤ f ≤ 133
75 ≤ f ≤ 133
75 ≤ f ≤ 133
75 ≤ f ≤ 100
75 ≤ f ≤ 167
75 ≤ f ≤ 133
75 ≤ f ≤ 133
75 ≤ f ≤ 133
All other combinations of values for A7–A11
(256MB), A7–A12 (512MB, 1GB), or A7–A13 (2GB) are
reserved for future use and/ or test modes. Test modes
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
10
MICRON [ MICRON TECHNOLOGY ]
