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MT16VDDT25664AG-265 参数 Datasheet PDF下载

MT16VDDT25664AG-265图片预览
型号: MT16VDDT25664AG-265
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR SDRAM UNBUFFERED DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 35 页 / 875 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号MT16VDDT25664AG-265的Datasheet PDF文件第27页浏览型号MT16VDDT25664AG-265的Datasheet PDF文件第28页浏览型号MT16VDDT25664AG-265的Datasheet PDF文件第29页浏览型号MT16VDDT25664AG-265的Datasheet PDF文件第30页浏览型号MT16VDDT25664AG-265的Datasheet PDF文件第31页浏览型号MT16VDDT25664AG-265的Datasheet PDF文件第33页浏览型号MT16VDDT25664AG-265的Datasheet PDF文件第34页浏览型号MT16VDDT25664AG-265的Datasheet PDF文件第35页  
256MB, 512MB, 1GB, 2GB (x64, DR)  
184-PIN DDR SDRAM UDIMM  
Ta b le 23: Se ria l Pre se n ce -De t e ct Ma t rix (2GB)  
“1”/0”: Serial Data, “driven to HIGH/driven to LOW”; notes appear on page 31  
BYTE  
DESCRIPTION  
ENTRY (VERSION)  
MT16VDDT25664A  
0
1
2
3
4
5
6
7
8
9
128  
80  
08  
07  
0E  
0B  
02  
40  
00  
04  
Number of SPD Bytes Used by Micron  
Total Number of Bytes in SPD Device  
Fundamental Memory Type  
256  
SDRAM DDR  
14  
Number of Row Addresses on Assembly  
Number of Column Addresses on Assembly  
Number of Physical Ranks on DIMM  
Module Data Width  
11  
2
64  
0
Module Data Width (Continued)  
Module Voltage Interface Levels  
SDRAM Cycle Time, tCK, (CAS Latency = 2.5) (See note  
1)  
SSTL 2.5V  
6ns (-335)  
7ns (-262/-26A)  
7.5ns (-265)  
60  
70  
75  
SDRAM Access From Clock, tAC, (CAS Latency = 2.5)  
10  
0.7ns (-335)  
0.75ns (-262/-26A/-265)  
70  
75  
11  
12  
13  
14  
15  
None  
00  
82  
08  
00  
01  
Module Configuration Type  
15.62µs, 7.8µs/SELF  
Refresh Rate/Type  
8
SDRAM Device Width (Primary DDR SDRAM)  
Error-Checking DDR SDRAM Data Width  
None  
1 clock  
Minimum Clock Delay, Back-to-Back Random Column  
Access  
16  
17  
18  
19  
20  
21  
22  
23  
Burst Lengths Supported  
Number of Banks on DDR SDRAM Device  
CAS Latencies Supported  
CS Latency  
2, 4, 8  
0E  
04  
0C  
01  
02  
20  
C0  
4
2, 2.5  
0
WE Latency  
1
SDRAM Module Attributes  
SDRAM Device Attributes: General  
SDRAM Cycle Time, tCK, (CAS Latency = 2)  
Unbuffered/Diff. Clock  
Fast/Concurrent AP  
7.5ns (-335/-262/-26A)  
10ns (-265)  
75  
A0  
24  
SDRAM Access From CK, tAC, (CAS Latency = 2)  
0.7ns (-335)  
0.75ns (-262/-26A/-265)  
70  
75  
SDRAM Cycle Time, tCK, (CAS Latency = 1.5)  
SDRAM Access From CK, tAC, (CAS Latency = 1.5)  
Minimum Row Precharge Time, tRP (see note 4)  
25  
26  
27  
N/A  
N/A  
00  
00  
18ns (-335)  
15ns (-262)  
20ns (-26A/-265)  
48  
3C  
50  
Minimum Row Active to Row Active, tRRD  
28  
29  
12ns (-335)  
15ns (-262/-26A/-265)  
30  
3C  
Minimum Ras# to CAS# Delay, tRCD (see note 4)  
18ns (-335)  
15ns (-262)  
20ns (-26A/-265)  
48  
3C  
50  
t
30  
42ns (-335)  
45ns (-262/-26A/-265)  
2A  
2D  
Minimum RAS# Pulse Width, RAS, (see note 2)  
31  
32  
1GB  
01  
Module Rank Density  
Address and Command Setup Time, tIS, (see note 3)  
0.8ns (-335)  
1.0ns (-262-26A/-265)  
80  
A0  
pdf: 09005aef80739fa5, source: 09005aef807397e5  
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2004 Micron Technology, Inc.  
32  
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