256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
No t e s
1. All voltages referenced to VSS.
25°C, VOUT (DC) = VDDQ/ 2, VOUT (peak to peak) =
0.2V. DM input is grouped with I/ O pins, reflecting
the fact that they are matched in loading.
2. Tests for AC timing, IDD, and electrical AC and DC
characteristics may be conducted at nominal ref-
erence/ supply voltage levels, but the related spec-
ifications and device operation are guaranteed for
the full voltage range specified.
12. For slew rates less than 1 V/ ns and greater than or
equal to 0.5 V/ ns. If slew rate is less than 0.5 V/ ns,
timing must be derated: tIS has an additional 50ps
per each 100mV/ ns reduction in slew rate from
3. Outputs m easured with equivalent load:
t
500mV/ ns, while IH is unaffected. If slew rate
VTT
exceeds 4.5V/ ns, functionality is uncertain.
13. The CK/ CK# input reference level (for timing ref-
erenced to CK/ CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/ CK# is VREF.
50
Ω
Reference
Point
Output
(VOUT
)
30pF
14. Inputs are not recognized as valid until VREF stabi-
lizes. Exception: during the period before VREF
stabilizes, CKE ≤ 0.3 x VDDQ is recognized as LOW.
15. The output tim ing reference level, as m easured at
the tim ing reference point indicated in Note 3, is
VTT.
4. AC timing and IDD tests m ay use a VIL-to-VIH
swing of up to 1.5V in the test environm ent, but
input timing is still referenced to VREF (or to the
crossing point for CK/ CK#), and parameter speci-
fications are guaranteed for the specified AC input
levels under norm al use conditions. The m ini-
m um slew rate for the input signals used to test
the device is 1V/ ns in the range between VIL(AC)
and VIH(AC).
t
16. tHZ and LZ transitions occur in the same access
tim e windows as valid data transitions. These
param eters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).
5. The AC and DC input level specifications are as
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
6. VREF is expected to equal VDDQ/ 2 of the transmit-
ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on VREF may not exceed ±2 percent of the
DC value. Thus, from VDDQ/ 2, VREF is allowed
±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the
nearest VREF bypass capacitor.
7. VTT is not applied directly to the device. VTT is a
system supply for signal termination resistors, is
expected to be set equal to VREF and must track
variations in the DC level of VREF.
8. IDD is dependent on output loading and cycle
rates. Specified values are obtained with m ini-
mum cycle time at CL = 2 for -262, and -26A, CL =
2.5 for -335 and -265 with the outputs open.
9. Enables on-chip refresh and address counters.
10. IDD specifications are tested after the device is
properly initialized, and is averaged at the defined
cycle rate.
17. The intent of the Don’t Care state after completion
of the postamble is the DQS-driven signal should
either be high, low, or high-Z and that any signal
transition within the input switching region must
follow valid input requirements. That is, if DQS
transitions high [above VIHDC (MIN)] then it must
not transition low (below VIHDC) prior to
tDQSH(MIN).
18. This is not a device limit. The device will operate
with a negative value, but system perform ance
could be degraded due to bus turnaround.
19. It is recom m ended that DQS be valid (HIGH or
LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this tim e,
t
depending on DQSS.
t
20. MIN (tRC or RFC) for IDD m easurements is the
smallest multiple of tCK that meets the minimum
t
absolute value for the respective parameter. RAS
(MAX) for IDD measurem ents is the largest m ulti-
t
ple of CK that m eets the m axim um absolute
value for tRAS.
21. The refresh period 64ms. This equates to an aver-
age refresh rate of 15.625µs (256MB) or 7.8125µs
(512MB, 1GB, 2GB). However, an AUTO REFRESH
com m and m ust be asserted at least once every
11. This parameter is sampled. VDD = +2.5V ±0.2V,
VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, TA =
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
20
©2004 Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
