256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
Ta b le 13: IDD Sp e cifica t io n s a n d Co n d it io n s – 512MB
DDR SDRAM Components only
Notes: 1–5, 8, 10, 14, 48; notes appear on pages 20–23; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V
MAX
-26A/
-265
PARAMETER/CONDITION
SYM
-335
-262
UNITS NOTES
IDD0a
1,032
1,032
992
mA
20, 42
OPERATING CURRENT: One device bank; Active-Precharge;
t
t
t
t
RC = RC (MIN); CK = CK (MIN); DQ, DM and DQS inputs
changing once per clock cyle; Address and control inputs
changing once every two clock cycles
IDD1a
1,392
1,312
1,192
mA
20, 42
OPERATING CURRENT: One device bank; Active -Read
t
t
Precharge; Burst = 4; tRC = RC (MIN); tCK = CK (MIN);
IOUT = 0mA; Address and control inputs changing once per
clock cycle
IDD2Pb
IDD2Fb
64
64
64
mA
mA
21, 28,
44
PRECHARGE POWER-DOWN STANDBY CURRENT: All device
t
banks idle; Power-down mode; tCK = CK (MIN); CKE =
(LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
800
720
720
45
t
tCK = CK MIN; CKE = HIGH; Address and other control
inputs changing once per clock cycle. VIN = VREF for DQ,
DQS, and DM
IDD3Pb
IDD3Nb
ACTIVE POWER-DOWN STANDBY CURRENT: One device
480
960
400
800
400
800
mA
mA
21, 28,
44
t
bank active; Power-down mode; tCK = CK (MIN); CKE =
LOW
40
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One
t
device bank; Active-Precharge; tRC = RAS (MAX);
t
tCK = CK (MIN); DQ, DM andDQS inputs changing twice per
clock cycle; Address and other control inputs changing once
per clock cycle
IDD4Ra
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One bank active; Address and control inputs changing once
1,432
1,432
1,232
1,232
1,232
1,232
mA
mA
20, 42
20
t
per clock cycle; tCK = CK (MIN); IOUT = 0mA
IDD4Wa
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One device bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and
DQS inputs changing twice per clock cycle
IDD5b
tREFC = tRFC (MIN)
4,080
96
3,760
96
3,760
96
mA
mA
20, 44
20, 44
AUTO REFRESH CURRENT
IDD5Ab
tREFC = 7.8125µs
SELF REFRESH CURRENT: CKE ≤ 0.2V
IDD6b
IDD7a
64
64
64
mA
mA
9
3,312
2,832
2,832
20, 43
OPERATING CURRENT: Four device bank interleaving READs
t
t
(BL = 4) with auto precharge, tRC = RC (MIN); tCK = CK
(MIN); Address and control inputs change only during Active
READ, or WRITE commands
NOTE:
a: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2p (CKE LOW) mode.
b: Value calculated reflects all module ranks in this operating condition.
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
15
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