256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
Ge n e ra l De scrip t io n
The
MT16VDDT3264A,
MT16VDDT6464A,
The pipelined, m ultibank architecture of DDR
SDRAM modules allows for concurrent operation,
thereby providing high effective bandwidth by hiding
row precharge and activation tim e.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2, Class II compatible. For more
information regarding DDR SDRAM operation, refer to
the 128Mb, 256Mb, 512Mb, or 1Gb DDR SDRAM com-
ponent data sheets.
MT16VDDT12864A, and MT16VDDT25664A are high-
speed CMOS, dynamic random-access, 256MB,
512MB, 1GB and 2GB memory modules organized in
x64 configuration. DDR SDRAM modules use inter-
nally configured quad-bank DDR SDRAM devices.
DDR SDRAM m odules use a double data rate archi-
tecture to achieve high-speed operation. Double data
rate architecture is essentially a 2n-prefetch architec-
ture with an interface designed to transfer two data
words per clock cycle at the I/ O pins. A single read or
write access for the DDR SDRAM module effectively
consists of a single 2n-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two corre-
sponding n-bit wide, one-half-clock-cycle data trans-
fers at the I/ O pins.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM during READs and by the m em ory
controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for
WRITEs.
DDR SDRAM modules operate from differential
clock inputs (CK and CK#); the crossing of CK going
HIGH and CK# going LOW will be referred to as the
positive edge of CK. Commands (address and control
signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and out-
put data is referenced to both edges of DQS, as well as
to both edges of CK.
Read and write accesses to DDR SDRAM m odules
are burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE com m and. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select devices bank; A0–A11 select
device row for 256MB; A0–A12 select device row for
512MB, 1GB; A0–A13 select device row for 2GB). The
address bits registered coincident with the READ or
WRITE command are used to select the device bank
and the starting device column location for the burst
access.
Se ria l Pre se n ce -De t e ct Op e ra t io n
DDR SDRAM modules incorporate serial presence-
detect (SPD). The SPD function is implemented using
a 2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
gram m ed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/ WRITE operations
between the m aster (system logic) and the slave
EEPROM device (DIMM) occur via a standard I2C bus
using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/ EEPROM addresses. Write protect (WP) is tied
to ground on the module, permanently disabling hard-
ware write protect.
Mo d e Re g ist e r De fin it io n
The mode register is used to define the specific
mode of operation of the DDR SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency and an operating m ode, as shown in
Figure 5, Mode Register Definition Diagram, on page 9.
The mode register is programmed via the MODE REG-
ISTER SET command (with BA0 = 0 and BA1 = 0) and
will retain the stored information until it is pro-
gram m ed again or the device loses power (except for
bit A8, which is self-clearing).
Reprogramming the mode register will not alter the
contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all device banks are idle and no bursts are in
progress, and the controller m ust wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.
DDR SDRAM modules provide for programmable
READ or WRITE burst lengths of 2, 4, or 8 locations. An
auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of
the burst access.
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
8
©2004 Micron Technology, Inc.
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