256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
and reserved states should not be used because
unknown operation or incompatibility with future ver-
sions may result.
Fig u re 7: Ext e n d e d Mo d e Re g ist e r
De fin it io n Dia g ra m
256MB Module
BA0
A8
A9
A6 A5 A4
A1
A0
Address Bus
BA1
A10
A7
A3 A2
A11
Ext e n d e d Mo d e Re g ist e r
The extended m ode register controls functions
beyond those controlled by the mode register; these
additional functions are DLL enable/ disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 7, Extended Mode Register
Definition Diagram. The extended mode register is
programmed via the LOAD MODE REGISTER com-
mand to the mode register (with BA0 = 1 and BA1 = 0)
and will retain the stored information until it is pro-
grammed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/ BA1 both LOW) to reset the DLL.
13
11
9
8
6
5
4
1
12
10
7
3
2
0
Extended Mode
Register (Ex)
1
1
0
1
Operating Mode
DS DLL
512MB and 1GB Modules
A8
A9
A6 A5 A4
A1
A0
Address Bus
BA1
A10
A7
A3 A2
BA0 A12 A11
14 13
11
9
8
6
5
4
1
12
10
7
3
2
0
Extended Mode
Register (Ex)
1
1
0
1
Operating Mode
DS DLL
2GB Module
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
The extended mode register m ust be loaded when
all device banks are idle and no bursts are in progress,
and the controller m ust wait the specified tim e before
initiating any subsequent operation. Violating either
of these requirements could result in unspecified oper-
ation.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Extended Mode
Register (Ex)
1
1
0
1
Operating Mode
DS DLL
DLL
E0
0
1
Enable
Disable
DLL En a b le /Disa b le
Drive Strength
E1
0
Normal
The DLL m ust be enabled for normal operation.
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled autom atically.) Any tim e the DLL is enabled,
200 clock cycles with CKE HIGH must occur before a
READ com m and can be issued.
E2
E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3
E1, E0
Valid
–
Operating Mode
Reserved
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
Reserved
NOTE:
1. BA1 and BA0 (E13 and E12 for 256MB, E14 and E13 for
512MB, 1GB, or E15 and E14 for 2GB) must be “0, 1” to
select the Extended Mode Register (vs. the base Mode
Register).
2. QFC# is not supported.
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
11
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