256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
41. The current Micron part operates below the slow-
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
42. Random addressing changing and 50 percent of
data changing at every transfer.
address and control inputs to remain stable.
Although IDD2F, IDD2N, and IDD2Q are similar,
IDD2F is “worst case.”
46. Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
47. Leakage num ber reflects the worst case leakage
possible through the m odule pin, not what each
memory device contributes.
43. Random addressing changing and 100 percent of
data changing at every transfer.
44. CKE must be active (high) during the entire tim e a
refresh command is executed. That is, from the
tim e the AUTO REFRESH com m and is registered,
CKE must be active at each rising clock edge, until
tREF later.
45. IDD2N specifies the DQ, DQS, and DM to be
driven to a valid high or low logic level. IDD2Q is
similar to IDD2F except IDD2Q specifies the
48. When an input signal is HIGH or LOW, it is
defined as a steady state logic HIGH or logic LOW.
t
49. The -335 speed grade will operate with RAS (MIN)
t
= 40ns and RAS (MAX) = 120,000ns at any slower
frequency.
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
23
©2004 Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
