256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
Ta b le 5:
Pin De scrip t io n s
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
63, 65, 154
WE#, CAS#, RAS#
Input
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
16, 17, 75, 76, 137, 138
CK0, CK0#, CK1,
CK1#, CK2, CK2#
Input Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the
positive edge of CK,and negative edge of CK#. Output data
(DQs and DQS) is referenced to the crossings of CK and CK#.
21, 111
CKE0, CKE1
Input Clock Enable: CKE HIGH activates and CKE LOW deactivates
the internal clock, input buffers and output drivers. Taking
CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any device bank). CKE is synchronous
for POWER-DOWN entry and exit, and for SELF REFRESH entry.
CKE is asynchronous for SELF REFRESH exit and for disabling
the outputs. CKE must be maintained HIGH throughout read
and write accesses. Input buffers (excluding CK, CK# and CKE)
are disabled during POWER-DOWN. Input buffers (excluding
CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input
but will detect an LVCMOS LOW level after VDD is applied and
until CKE is first brought HIGH. After CKE is brought HIGH, it
becomes an SSTL_2 input only.
157, 158
52, 59
S0#, S1#
Input
Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
BA0, BA1
Input
Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
27, 29, 32, 37, 41, 43, 48,
115 (512MB, 1GB, 2GB), 118,
122, 125, 130, 141, 167 (2GB)
A0–A11
(256MB)
A0–A12
Input Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out of
the memory array in the respective device bank. A10 sampled
during a PRECHARGE command determines whether the
PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH). The
address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
(512MB, 1GB)
A0–A13
(2GB)
5, 14, 25, 36, 56, 67, 78, 86
DQS0–DQS7
DM0–DM7
Input/
Output
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
97, 107, 119, 129, 149, 159,
169, 177
Input Data Write Mask: DM LOW allows WRITE operation. DM HIGH
blocks WRITE operation. DM lines do not affect READ
operation.
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
4
©2004 Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
