256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
In it ia liza t io n
To ensure device operation the DRAM must be ini-
tialized as described below:
Fig u re 11: In it ia liza t io n Flo w Dia g ra m
Step
1. Simultaneously apply power to VDD and VDDQ.
2. Apply VREF and then VTT power.
3. Assert and hold CKE at a LVCMOS logic low.
4. Provide stable CLOCK signals.
1
2
V
DD and VDDQ Ramp
Apply VREF and VTT
5. Wait at least 200µs.
6. Bring CKE high and provide at least one NOP or
DESELECT command. At this point the CKE input
changes from a LVCMOS input to a SSTL2 input
only and will remain a SSTL_2 input unless a
power cycle occurs.
3
CKE must be LVCMOS Low
4
Apply stable CLOCKs
5
Wait at least 200us
7. Perform a PRECHARGE ALL command.
t
8. Wait at least RP time, during this time NOPs or
6
Bring CKE High with a NOP command
DESELECT commands must be given.
9. Using the LMR command program the Extended
Mode Register (E0 = 0 to enable the DLL and E1 =
0 for norm al drive or E1 = 1 for reduced drive, E2
through En must be set to 0; where n = most sig-
nificant bit).
7
PRECHARGE ALL
t
8
Assert NOP or DESELECT for RP time
t
10. Wait at least MRD time, only NOPs or DESELECT
9
Configure Extended Mode Register
commands are allowed.
11. Using the LMR command program the Mode Reg-
ister to set operating param eters and to reset the
DLL. Note at least 200 clock cycles are required
between a DLL reset and any READ com mand.
t
10
11
12
13
14
15
16
17
18
19
20
21
Assert NOP or DESELECT for MRD time
Configure Load Mode Register and reset DLL
t
12. Wait at least MRD time, only NOPs or DESELECT
commands are allowed.
t
Assert NOP or DESELECT for MRD time
13. Issue a PRECHARGE ALL command.
t
14. Wait at least RP tim e, only NOPs or DESELECT
PRECHARGE ALL
commands are allowed.
15. Issue an AUTO REFRESH comm and (Note this
may be moved prior to step 13).
t
Assert NOP or DESELECT for RP time
t
16. Wait at least RFC time, only NOPs or DESELECT
commands are allowed.
Issue AUTO REFRESH command
17. Issue an AUTO REFRESH comm and (Note this
may be moved prior to step 13).
t
Assert NOP or DESELECT commands for RFC
t
18. Wait at least RFC time, only NOPs or DESELECT
commands are allowed.
Issue AUTO REFRESH command
19. Although not required by the Micron device,
JEDEC requires a LMR command to clear the DLL
bit (set M8 = 0). If a LMR command is issued the
same operating parameters should be utilized as
in step 11.
t
Assert NOP or DESELECT for RFC time
Optional LMR command to clear DLL bit
t
20. Wait at least MRD time, only NOPs or DESELECT
t
commands are allowed.
Assert NOP or DESELECT for MRD time
21. At this point the DRAM is ready for any valid com-
mand. Note 200 clock cycles are required between
step 11 (DLL Reset) and any READ command.
DRAM is ready for any valid command
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
24
MICRON [ MICRON TECHNOLOGY ]
