512MB, 1GB (x64, DR) 200-Pin DDR SODIMM
Ele ct rica l Sp e cifica t io n s
IDD Sp e cifica t io n s
Ta b le 9:
IDD Sp e cifica t io n s a n d Co n d it io n s – 512MB (Die Re viso n K)
Values are shown for the MT46V32M8 DDR SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet
Pa ra m e t e r/Co n d it io n
Sym b o l
-40B
-335
Un it s
Op e ra t in g o n e b a n k a ct ive -p re ch a rg e cu rre n t : One device
IDD01
832
752
mA
t
t
bank; Active-precharge; tRC = RC (MIN); tCK = CK (MIN); DQ, DM,
and DQS inputs changing once per clock cycle; Address and control
inputs changing once every two clock cycles
Op e ra t in g o n e b a n k a ct ive -re a d -p re ch a rg e cu rre n t : One device
IDD11
992
952
mA
t
bank; Active-read-precharge; BL = 4; tRC = RC (MIN);
t
tCK = CK (MIN); IOUT = 0mA; Address and control inputs changing
once per clock cycle
Pre ch a rg e p o w e r-d o w n st a n d b y cu rre n t : All device banks idle;
IDD2P2
IDD2F2
64
64
mA
mA
t
Power-down mode; tCK = CK (MIN); CKE = (LOW)
Id le st a n d b y cu rre n t : CS# = HIGH; All device banks are idle;
800
800
t
tCK = CK (MIN); CKE = HIGH; Address and other control inputs
changing once per clock cycle. VIN = VREF for DQ, DQS, and DM
Act ive p o w e r-d o w n st a n d b y cu rre n t : One device bank active;
IDD3P2
IDD3N2
560
960
480
880
mA
mA
t
Power-down mode; tCK = CK (MIN); CKE = LOW
Act ive st a n d b y cu rre n t : CS# = HIGH; CKE = HIGH; One device
t
t
bank active; tRC = RAS (MAX); tCK = CK (MIN); DQ, DM, and DQS
inputs changing twice per clock cycle; Address and other control
inputs changing once per clock cycle
Op e ra t in g b u rst re a d cu rre n t : BL = 2; Continuous burst reads;
IDD4R1
1,472
1,472
1,132
1,312
mA
mA
One device bank active; Address and control inputs changing once
t
per clock cycle; tCK = CK (MIN); IOUT = 0mA
Op e ra t in g b u rst w rit e cu rre n t : BL = 2; Continuous burst writes;
IDD4W1
One device bank active; Address and control inputs changing once
t
per clock cycle; tCK = CK (MIN); DQ, DM, and DQS inputs changing
twice per clock cycle
t
Au t o re fre sh b u rst cu rre n t
tREFC = RFC (MIN)
tREFC = 7.8125µs
Standard
IDD52
IDD5A2
IDD62, 3
IDD6A2, 3
IDD71
2,560
96
2,560
96
mA
mA
mA
mA
mA
Se lf re fre sh cu rre n t : CKE ≤ 0.2V
64
64
Low power
32
32
Op e ra t in g b a n k in t e rle a ve re a d cu rre n t : Four device bank
2,352
2,192
interleaving reads (BL = 4) with auto precharge;
t
tRC = (MIN) tRC allowed; tCK = CK (MIN); Address and control
inputs change only during active READ or WRITE commands
Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks are
in IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
3. The standard module guarantees IDD6 and the low-power module guarantees IDD6A.
PDF: 09005aef80a77a90/Source: 09005aef80a646bc
DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved
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