欢迎访问ic37.com |
会员登录 免费注册
发布采购

MT16VDDF6464H 参数 Datasheet PDF下载

MT16VDDF6464H图片预览
型号: MT16VDDF6464H
PDF下载: 下载PDF文件 查看货源
内容描述: 小外形的DDR SDRAM DIMM [SMALL-OUTLINE DDR SDRAM DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 31 页 / 552 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号MT16VDDF6464H的Datasheet PDF文件第2页浏览型号MT16VDDF6464H的Datasheet PDF文件第3页浏览型号MT16VDDF6464H的Datasheet PDF文件第4页浏览型号MT16VDDF6464H的Datasheet PDF文件第5页浏览型号MT16VDDF6464H的Datasheet PDF文件第6页浏览型号MT16VDDF6464H的Datasheet PDF文件第7页浏览型号MT16VDDF6464H的Datasheet PDF文件第8页浏览型号MT16VDDF6464H的Datasheet PDF文件第9页  
512MB, 1GB (x64)
200-PIN DDR SODIMM
SMALL-OUTLINE
DDR SDRAM DIMM
Features
• 200-pin, small-outline, dual in-line memory
module (SODIMM)
• Fast data transfer rates: PC1600, PC2100, and PC2700
• Utilizes 200 MT/s, 266 MT/s, or 333 MT/s DDR
SDRAM components
• 512MB (64 Meg x 64), 1GB (128 Meg x 64)
• V
DD
= V
DD
Q = +2.5V
• V
DDSPD
= +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 7.8125µs maximum average periodic refresh interval
• Serial Presence Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
MT16VDDF6464H – 512MB
MT16VDDF12864H – 1GB
For the latest data sheet, please refer to the Micron
â
Web
site:
Figure 1: 200-Pin SODIMM (MO-224)
512MB Module
1GB Module
OPTIONS
MARKING
G
• Package
200-pin SODIMM (standard)
200-pin SODIMM (lead-free)
• Frequency/CAS Latency
167 MHz (333 MT/s) CL = 2.5
133 MHz (266 MT/s) CL = 2
133 MHz (266 MT/s) CL = 2
133 MHz (266 MT/s) CL = 2.5
100 MHz (200 MT/s) CL = 2
NOTE:
Y
-335
-262
-26A
-265
-202
1. Contact factory for availability of lead-free prod-
ucts.
2. CL = CAS (READ) latency.
Table 1:
Address Table
512MB
1GB
8K
8K (A0–A12)
4 (BA0, BA1)
64 Meg x 8
2K (A0–A9, A11)
2 (S0#, S1#)
8K
8K (A0–A12)
4 (BA0, BA1)
32 Meg x 8
1K (A0–A9)
2 (S0#, S1#)
Refresh Count
Device Row Addressing
Device Bank Addressing
Device Configuration
Device Column Addressing
Module Rank Addressing
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
1
©2003 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.