512MB, 1GB (x64)
200-PIN DDR SODIMM
t
t
30. tHP min is the lesser of CL minimum and CH
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
f. The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
31. READs and WRITEs with auto precharge are not
allowed to be issued until tRAS(MIN) can be satis-
fied prior to the internal precharge command
being issued.
34. The voltage levels used are derived from a mini-
mum VDD level and the referenced test load. In
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
35. VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a
pulse widthꢀ? 3ns and the pulse width can not be
greater than 1/3 of the cycle rate. VIL undershoot:
VIL (MIN) = -1.5V for a pulse width ?ꢀ 3ns and the
pulse width can not be greater than 1/3 of the
cycle rate.
32. Any positive glitch must be less than 1/3 of the
clock and not more than +400mV or 2.9V, which-
ever is less. Any negative glitch must be less than
1/3 of the clock cycle and not exceed either -
300mV or 2.2V, whichever is more positive.
33. Normal Output Drive Curves:
a. The full variation in driver pull-down current
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 9,
Pull-Down Characteristics.
b. The variation in driver pull-down current
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 9, Pull-Down Characteristics.
c. The full variation in driver pull-up current
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 10,
Pull-Up Characteristics.
d. The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
10, Pull-Up Characteristics.
e. The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
36. VDD and VDDQ must track each other.
37. This maximum value is derived from the refer-
enced test load. In practice, the values obtained
in a typical terminated design may reflect up to
t
t
310ps less for HZ(MAX) and the last DVW. HZ
t
t
(MAX) will prevail over DQSCK (MAX) + RPST
(MAX) condition. tLZ (MIN) will prevail over
tDQSCK (MIN) + tRPRE (MAX) condition.
38. For slew rates greater than 1V/ns the (LZ) transi-
tion will start about 310ps earlier.
39. During Initialization, VDDQ, VTT, and VREF must
be equal to or less than VDD + 0.3V. Alternatively,
VTT may be 1.35V maximum during power up,
even if VDD/VDDQ are 0.0V, provided a minimum
of 42ꢁ of series resistance is used between the VTT
supply and the input pin.
40. The current Micron part operates below the slow-
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
Figure 9: Pull-Down Characteristics
Figure 10: Pull-Up Characteristics
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
22
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