512MB, 1GB (x64)
200-PIN DDR SODIMM
41. For -265, -26A, -262 and -335, IDD3N is specified to
be 35mA at 100 MHz.
42. Random addressing changing and 50 percent of
data changing at every transfer.
similar to IDD2F except IDD2Q specifies the
address and control inputs to remain stable.
Although IDD2F, IDD2N, and IDD2Q are similar,
IDD2F is “worst case.”
43. Random addressing changing and 100 percent of
data changing at every transfer.
44. CKE must be active (high) during the entire time a
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
46. Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
47. Leakage number reflects the worst case leakage
possible through the module pin, not what each
memory device contributes.
tREF later.
48. When an input signal is HIGH or LOW, it is
defined as a steady state logic HIGH or LOW.
45. IDD2N specifies the DQ, DQS, and DM to be
driven to a valid high or low logic level. IDD2Q is
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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