512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 14: Capacitance
Note: 11; notes appear notes appear on pages 20–23
PARAMETER
SYMBOL
MIN MAX
UNITS
CIO
CI1
CI2
7
9
pF
pF
pF
Input/Output Capacitance: DQ, DQS,DM
24
12
40
20
Input Capacitance: Command and Address, RAS#, CAS#, WE#
Input Capacitance:CK, CK#, CKE, S#
Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC
Operating Conditions (-335, -262)
Notes: 1–5, 12–15, 29, 40; notes appear on pages 20–23; 0°Cꢀ? TA ? +70°C; VDD = VDDQ = +2.5V 0.2V
AC CHARACTERISTICS
-335
MAX
-262
MAX
PARAMETER
SYMBOL MIN
MIN
-0.75
0.45
0.45
7.5
UNITS NOTES
tAC
tCH
tCL
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
-0.70
0.45
0.45
6
+0.70
0.55
0.55
13
+0.75
0.55
0.55
13
ns
tCK
26
tCK
26
tCK (2.5)
tCK (2)
tDH
CL=2.5
CL=2
ns
ns
ns
ns
ns
ns
40, 46
40, 46
23, 27
23, 27
27
7.5
13
7.5
13
0.45
0.45
1.75
-0.60
0.35
0.35
0.5
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
tDS
0.5
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
1.75
-0.75
0.35
0.35
+0.60
+0.75
tCK
tCK
DQS input low pulse width
0.4
0.5
ns
22, 23
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
tCK
tCK
tCK
0.75
0.20
0.20
1.25
0.75
0.20
0.20
1.25
tDSH
tHP
tCH,tCL
+0.70
tCH,tCL
+0.75
ns
8
tHZ
ns
ns
ns
16, 37
16, 38
12
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
tLZ
tIHF
-0.70
0.75
-0.75
0.90
tISF
tIHS
tISS
0.75
0.8
0.90
1
ns
ns
ns
12
12
12
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
0.8
1
tIPW
tMRD
tQH
tQHS
tRAS
tRAP
2.2
12
2.2
15
ns
ns
ns
ns
ns
ns
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
tHP -tQHS
tHP -tQHS
22, 23
31
0.75
0.75
42
18
70,000
40
15
120,000
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
16
MICRON [ MICRON TECHNOLOGY ]
