512MB, 1GB (x64)
200-PIN DDR SODIMM
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/ BA1 both LOW) to reset the DLL.
Figure 7: Extended Mode Register
Definition Diagram
A8
A6 A5 A4
A1
A0
Address Bus
BA1
A10
A7
A3 A2
BA0 A12 A11
A9
The extended mode register must be loaded when
all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either of
these requirements could result in unspecified opera-
tion.
14 13
11
9
8
6
5
4
1
12
10
7
3
2
0
Extended Mode
Register (Ex)
1
1
0
1
Operating Mode
DS DLL
DLL
E0
0
Enable
Disable
1
DLL Enable/Disable
The DLL must be enabled for normal operation.
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled,
200 clock cycles must occur before a READ command
can be issued.
Drive Strength
Normal
E1
0
1
Reduced
E22
0
E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3
E1, E0
Valid
–
Operating Mode
Reserved
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
–
Reserved
NOTE:
1. BA1 and BA0 (E14 and E13) must be “0, 1” to select the
Extended Mode Register (vs. the base Mode Register).
2. The QFC# option is not supported.
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
11
MICRON [ MICRON TECHNOLOGY ]
