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MT16VDDF6464HG-202 参数 Datasheet PDF下载

MT16VDDF6464HG-202图片预览
型号: MT16VDDF6464HG-202
PDF下载: 下载PDF文件 查看货源
内容描述: 小外形的DDR SDRAM DIMM [SMALL-OUTLINE DDR SDRAM DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 31 页 / 552 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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512MB, 1GB (x64)  
200-PIN DDR SODIMM  
Table 19: Serial Presence-Detect EEPROM DC Operating Conditions  
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V  
PARAMETER/CONDITION  
SYMBOL  
MIN  
MAX  
UNITS  
VDDSPD  
VIH  
VIL  
2.3  
3.6  
V
V
SUPPLY VOLTAGE  
VDD Pꢀ0.7 VDD + 0.5  
INPUT HIGH VOLTAGE: Logic 1; All inputs  
INPUT LOW VOLTAGE: Logic 0; All inputs  
-1  
VDD Pꢀ0.3  
V
VOL  
ILI  
0.4  
10  
10  
30  
2
V
OUTPUT LOW VOLTAGE: IOUT = 3mA  
µA  
µA  
µA  
mA  
INPUT LEAKAGE CURRENT: VIN = GND to VDD  
OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD  
STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VDD or VSS  
POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz  
ILO  
ISB  
ICC  
Table 20: Serial Presence-Detect EEPROM AC Operating Conditions  
All voltages referenced to VSS; VDDSPD = +2.3V TO +3.6V  
PARAMETER/CONDITION  
SYMBOL  
MIN MAX UNITS  
NOTES  
tAA  
tBUF  
0.2  
1.3  
0.9  
µs  
µs  
1
SCL LOW to SDA data-out valid  
Time the bus must be free before a new transition can start  
Data-out hold time  
tDH  
200  
ns  
tF  
300  
ns  
2
SDA and SCL fall time  
tHD:DAT  
tHD:STA  
tHIGH  
tI  
tLOW  
tR  
fSCL  
tSU:DAT  
tSU:STA  
tSU:STO  
tWRC  
0
µs  
Data-in hold time  
0.6  
0.6  
µs  
Start condition hold time  
Clock HIGH period  
µs  
50  
ns  
Noise suppression time constant at SCL, SDA inputs  
Clock LOW period  
1.3  
µs  
0.3  
µs  
2
SDA and SCL rise time  
400  
KHz  
ns  
SCL clock frequency  
100  
0.6  
0.6  
Data-in setup time  
µs  
3
4
Start condition setup time  
Stop condition setup time  
WRITE cycle time  
µs  
10  
ms  
NOTE:  
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising  
edge of SDA.  
2. This parameter is sampled.  
3. For a reSTART condition, or following a WRITE cycle.  
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of  
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA  
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.  
09005aef80a646bc  
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2003 Micron Technology, Inc.  
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