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MT16LSDT6464AG-10E 参数 Datasheet PDF下载

MT16LSDT6464AG-10E图片预览
型号: MT16LSDT6464AG-10E
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM模块 [SYNCHRONOUS DRAM MODULE]
分类和应用: 动态存储器
文件页数/大小: 24 页 / 609 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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256MB / 512MB (x64)  
168-PIN SDRAM DIMMs  
Co m m a n d s  
The Truth Table provides a quick reference of avail-  
able commands. This is followed by written descrip-  
tion of each com m and. For a m ore detailed descrip-  
tion of commands and operations, refer to the 256Mb  
SDRAM component data sheet.  
Ta b le 9:  
Tru t h Ta b le – SDRAM Co m m a n d s a n d DQMB Op e ra t io n  
CKE is HIGH for all commands shown except SELF REFRESH; notes appear following the Truth Table  
NAME (FUNCTION)  
CS# RAS# CAS# WE# DQMB  
ADDR  
DQ  
NOTES  
H
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
X
X
X
X
X
COMMAND INHIBIT (NOP)  
X
NO OPERATION (NOP)  
X
Bank/Row  
Bank/Col  
Bank/Col  
X
1
2
2
ACTIVE (Select bank and activate row)  
READ (Select bank and column, and start READ burst)  
H
H
L/H  
L/H  
X
L
Valid  
WRITE (Select bank and column, and start WRITE  
burst)  
BURST TERMINATE  
L
L
L
H
L
L
H
H
L
L
L
X
X
X
X
Code  
X
Active  
PRECHARGE (Deactivate row in bank or banks)  
X
X
3
AUTO REFRESH or SELF REFRESH  
(Enter self refresh mode)  
H
4, 5  
L
L
L
L
X
L
Op-code  
X
6
7
7
LOAD MODE REGISTER  
Active  
High-Z  
Write Enable/Output Enable  
Write Inhibit/Output High-Z  
H
NOTE:  
1. A0–A12 provide row address; BA0–BA1 determine which device bank is made active.  
2. A0–A9 provide column address; A10 HIGH enables the auto-precharge feature (nonpersistent), while A10 LOW dis-  
ables the auto-precharge feature; BA0-BA1 determine which device bank is being read from or written to.  
3. A10 LOW: BA0–BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged  
and BA0, BA1 are “Dont Care.”  
4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.  
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Dont Care” except for CKE.  
6. A0–A11 define the op-code written to the mode register and A12 should be driven LOW.  
7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).  
32,64 Meg x 64 SDRAM DIMMs  
SD8_16C32_64x64AG_C.fm - Rev. C 11/02  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2002, Micron Technology Inc.  
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