256MB / 512MB (x64)
168-PIN SDRAM DIMMs
CAS La t e n cy
Op e ra t in g Mo d e
The CAS latency is the delay, in clock cycles,
between the registration of a READ com m and and the
availability of the first piece of output data. The latency
can be set to two or three clocks.
The norm al operating mode is selected by setting
M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/ or test
modes. The programmed burst length applies to both
READ and WRITE bursts.
If a READ com m and is registered at clock edge n,
and the latency is m clocks, the data will be available
by clock edge n + m. The DQs will start driving as a
result of the clock edge one cycle earlier (n + m - 1),
and provided that the relevant access tim es are m et,
the data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all rele-
vant access tim es are m et, if a READ com m and is regis-
tered at T0 and the latency is program m ed to two
clocks, the DQs will start driving after T1 and the data
will be valid by T2, as shown in Figure 6, CAS Latency
Diagram. Table 8, CAS Latency Table, indicates the
operating frequencies at which each CAS latency set-
ting can be used.
Test modes and reserved states should not be used
because unknown operation or incompatibility with
future versions may result.
Writ e Bu rst Mo d e
When M9 = 0, the burst length programm ed via M0–
M2 applies to both READ and WRITE bursts; when
M9 = 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (non-
burst) accesses.
Ta b le 8:
CAS La t e n cy Ta b le
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
ALLOWABLE OPERATING
CLOCK FREQUENCY (MHZ)
SPEED
CAS LATENCY = 2 CAS LATENCY = 3
? 133 ? 143
Fig u re 6: CAS La t e n cy Dia g ra m
-13E
-133
-10E
T0
T1
T2
T3
? 100
? 100
? 133
CLK
NA
COMMAND
READ
NOP
t
NOP
t
LZ
OH
DOUT
DQ
t
AC
CAS Latency = 2
T0
T1
T2
T3
T4
CLK
COMMAND
READ
NOP
NOP
NOP
t
t
LZ
OH
DOUT
DQ
t
AC
CAS Latency = 3
DON’T CARE
UNDEFINED
32,64 Meg x 64 SDRAM DIMMs
SD8_16C32_64x64AG_C.fm - Rev. C 11/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
10
MICRON [ MICRON TECHNOLOGY ]
