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MT16LSDF6464LHG-10E 参数 Datasheet PDF下载

MT16LSDF6464LHG-10E图片预览
型号: MT16LSDF6464LHG-10E
PDF下载: 下载PDF文件 查看货源
内容描述: [SMALL-OUTLINE SDRAM MODULE]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 22 页 / 476 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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256MB, 512MB (x64, DR)  
144-PIN SDRAM SODIMM  
Commands  
The Truth Table provides a quick reference of avail-  
able commands. This is followed by written descrip-  
description of commands and operations, refer to the  
128Mb or 256Mb SDRAM component data sheet.  
tion of each command. For  
a more detailed  
Table 9:  
Truth Table – SDRAM Commands and DQMB Operation  
CKE is HIGH for all commands shown except SELF REFRESH  
NAME (FUNCTION)  
CS# RAS# CAS# WE# DQMB  
ADDR  
DQ  
NOTES  
H
X
H
L
X
H
H
L
X
H
H
H
X
X
X
X
X
X
X
X
COMMAND INHIBIT (NOP)  
L
L
L
X
NO OPERATION (NOP)  
Bank/Row  
Bank/Col  
1
2
ACTIVE (select bank and activate row)  
READ (select bank and column, and start READ burst)  
L/H8  
H
L/H8  
X
L
H
L
L
Bank/Col Valid  
2
WRITE (select bank and column, and start WRITE burst)  
L
L
L
H
L
H
H
L
L
L
X
Code  
X
Active  
BURST TERMINATE  
X
X
X
3
PRECHARGE (deactivate row in bank or banks)  
L
H
X
4, 5  
AUTO REFRESH or SELF REFRESH  
(enter self refresh mode)  
L
L
L
L
X
L
Op-code  
X
6
7
7
LOAD MODE REGISTER  
Active  
High-Z  
Write enable/output enable  
Write inhibit/output High-Z  
H
NOTE:  
1. A0–A11 (256MB) or A0–A12 (512MB) provide device row address, and BA0, BA1 determine which device bank is made  
active.  
2. A0–A9 (256MB and 512MB) provide device column address; A10 HIGH enables the auto precharge feature (nonpersis-  
tent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which device bank is being read from or  
written to.  
3. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and  
BA0, BA1 are “Don’t Care.”  
4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.  
5. Internal refresh counter controls row addressing; all inputs and I/Os are Don’t Careexcept for CKE.  
6. A0–A11 define the op-code written to the mode register; for the 256MB and 512MB, A12 should be driven low.  
7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).  
pdf: 09005aef807924d2, source: 09005aef807924f1  
SDF16C32_64x64HG.fm - Rev. E 4/06 EN  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2006 Micron Technology, Inc. All rights reserved.  
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