256MB, 512MB (x64, DR)
144-PIN SDRAM SODIMM
Operating Mode
Table 8:
CL Table
The normal operating mode is selected by setting
M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with
future versions may result.
ALLOWABLE OPERATING
CLOCK FREQUENCY (MHz)
SPEED
CL = 2
CL = 3
-13E
-133
-10E
≤ 133
≤ 100
≤ 100
< 143
< 133
≤ NA
Write Burst Mode
When M9 = 0, the burst length programmed via M0-
M2 applies to both READ and WRITE bursts; when
M9 = 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (non-
burst) accesses.
pdf: 09005aef807924d2, source: 09005aef807924f1
SDF16C32_64x64HG.fm - Rev. E 4/06 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
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