512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Electrical Specifications
Table 9:
DDR2 IDD Specifications and Conditions – 2GB
Values shown for DDR2 SDRAM components only
Parameter/Condition
Symbol -80E -667 -53E -40E Units
Operating one device bank active-precharge current; tCK = tCK (IDD),
tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
IDD0a
856
776
856
696
816
616
696
mA
mA
Operating one device bank active-read-precharge current; IOUT =
0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS =
tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data pattern is same as
IDD4W
Precharge power-down current; All device banks idle; tCK = tCK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
IDD1a
936
112
IDD2Pb
112
880
960
112
656
720
112
560
640
mA
mA
mA
Precharge quiet standby current; All device banks idle; tCK = tCK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
IDD2Qb 1,040
Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data IDD2Nb 1,120
bus inputs are switching
Active power-down current; All device banks open; tCK Fast PDN exit
720
640
160
480
160
400
160
mA
mA
= tCK (IDD); CKE is LOW; Other control and address bus
inputs are stable; Data bus inputs are floating
MR[12] = 0
IDD3Pb
Slow PDN exit
MR[12] = 1
160
Active standby current; All device banks open; tCK = tCK (IDD), tRAS =
tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Other control and address bus inputs are switching; Data bus
inputs are switching
IDD3Nb 1,200 1,120
880
720
mA
mA
Operating burst write current; All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
IDD4Wa 1,536 1,336 1,096 936
IDD4Ra 1,576 1,336 1,216 936
Operating burst read current; All device banks open; Ccontinuous burst
reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are
switching
mA
Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC
(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other
control and address bus inputs are switching; Data bus inputs are
switching
IDD5b
IDD6b
4,480 4,160 4,000 3,520
mA
mA
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
112
112
112
112
Operating device bank interleave read current; All device banks
interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 ×
tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD
(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are stable during DESELECTs; Data bus inputs are switching; See
IDD7 conditions in component data sheet for detail
IDD7a
2,736 2,456 2,376 2,136
mA
Notes: 1. a = Value calculated as one module rank in this operating condition, and all other module
ranks in IDD2P (CKE LOW).
2. b = Value calculated reflects all module ranks in this operating condition.
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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