512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Electrical Specifications
Table 7:
DDR2 IDD Specifications and Conditions – 512MB
Values shown for DDR2 SDRAM components only
Parameter/Condition
Symbol -667
-53E
-40E Units
Operating one device bank active-precharge current; tCK = tCK (IDD),
tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
IDD0a
680
760
680
640
720
mA
mA
Operating one device bank active-read-precharge current; IOUT = 0mA; BL
= 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD),
tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data pattern is same as IDD4W
IDD1a
760
Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
IDD2Pb
IDD2Qb
IDD2Nb
80
80
80
mA
mA
mA
560
640
560
560
400
480
Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH,
S# is HIGH; Other control and address bus inputs are switching; Data bus inputs
are switching
Active power-down current; All device banks open; tCK = tCK Fast PDN exit
480
96
400
96
320
96
mA
mA
(IDD); CKE is LOW; Other control and address bus inputs are
stable; Data bus inputs are floating
MR[12] = 0
IDD3Pb
IDD3Nb
Slow PDN exit
MR[12] = 1
Active standby current; All device banks open; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are
switching
800
640
480
mA
mA
mA
Operating burst write current; All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP =
tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
are switching; Data bus inputs are switching
IDD4Wa 1,560 1,320 1,040
Operating burst read current; All device banks open; Continuous burst reads,
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
IDD4Ra
1,480 1,240
960
Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
IDD5b
IDD6b
2,880 2,720 2,640
mA
mA
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
80
80
80
Operating device bank interleave read current; All device banks
interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK
(IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are stable during
DESELECTs; Data bus inputs are switching; See IDD7 conditions in component
data sheet for detail
IDD7a
2,040 1,960 1,880
mA
Notes: 1. a = Value calculated as one module rank in this operating condition, and all other module
ranks in IDD2P (CKE LOW).
2. b = Value calculated reflects all module ranks in this operating condition.
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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