M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
Description
1
Description
The M58BW016DT, M58BW016DB, M58BW016FT and M58BW016FB are 16-Mbit non-
volatile Flash memories that can be erased electrically at the block level and programmed
in-system on a double-word basis using a 2.7 V to 3.6 V V
DD
supply for the circuit and a
V
DDQ
supply down to 2.4 V for the input and output buffers. Optionally a 12 V V
PP
supply
can be used to provide fast program and erase for a limited time and number of
program/erase cycles.
The devices support asynchronous (latch controlled and page read) and synchronous bus
operations. The synchronous burst read interface allows a high data transfer rate controlled
by the burst clock, K, signal. It is capable of bursting fixed or unlimited lengths of data. The
burst type, latency and length can be configured and can be easily adapted to a large
variety of system clock frequencies and microprocessors. All writes are asynchronous. On
power-up the memory defaults to read mode with an asynchronous bus.
The devices have a boot block architecture with an array of 8 parameter blocks of 64 Kbits
each and 31 main blocks of 512 Kbits each. In the M58BW016DT and M58BW016FT the
parameter blocks are located at the top of the address space whereas in the M58BW016DB
and M58BW016FB, they are located at the bottom.
Program and erase commands are written to the command interface of the memory. An on-
chip program/erase controller simplifies the process of programming or erasing the memory
by taking care of all of the special operations that are required to update the memory
contents. The end of a program or erase operation can be detected and any error conditions
identified in the status register. The command set required to control the memory is
consistent with JEDEC standards.
Erase can be suspended in order to perform either read or program in any other block and
then resumed. Program can be suspended to read data in any other block and then
resumed. Each block can be programmed and erased over 100,000 cycles.
All blocks are protected during power-up.
The M58BW016DT, M58BW016DB, M58BW016FT and M58BW016FB feature two different
levels of block protection to avoid unwanted program/erase operations:
The WP pin offers an hardware protection on two of the parameter blocks and all of the
main blocks
All program or erase operations are blocked when Reset, RP, is held Low. A
reset/power-down mode is entered when the RP input is Low. In this mode the power
consumption is lower than in the normal standby mode, the device is write protected
and both the status and the burst configuration registers are cleared. A recovery time is
required when the RP input goes High.
The memory is offered in a PQFP80 (14 x 20 mm) and LBGA80 (10 × 12 mm) package.
The memories are supplied with all the bits erased (set to ’1’).
In the present document, M58BW016DT, M58BW016DB, M58BW016FT and
M58BW016FB will be referred to as M58BW016 unless otherwise specified.
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MICRON [ MICRON TECHNOLOGY ]
