Bus operations
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
3.3.6
3.3.7
3.3.8
Valid clock edge bit (M6)
The valid clock edge bit, M6, is used to configure the active edge of the Clock, K, during
synchronous burst read operations. When the valid clock edge bit is ’0’ the falling edge of
the clock is the active edge; when the valid clock edge bit is ’1’ the rising edge of the clock is
active.
Wrap burst bit (M3)
The burst reads can be confined inside the 4 or 8 double-word boundary (wrap) or
overcome the boundary (no wrap). The wrap burst bit is used to select between wrap and no
wrap. When the wrap burst bit is set to ‘0’ the burst read wraps; when it is set to ‘1’ the burst
read does not wrap.
Burst length bit (M2-M0)
The burst length bits set the maximum number of double-words that can be output during a
synchronous burst read operation before the address wraps. Burst lengths of 4 or 8 are
available for both the sequential and interleaved burst types, and a continuous burst is
available for the sequential type.
Table 7: Burst configuration register gives the valid combinations of the burst length bits that
the memory accepts; Table 8: Burst type definition, gives the sequence of addresses output
from a given starting address for each length.
If either a continuous or a no wrap burst read has been initiated the device will output data
synchronously. Depending on the starting address, the device activates the valid data ready
output to indicate that a delay is necessary before the data is output. If the starting address
is aligned to an 8 double-word boundary, the continuous burst mode will run without
activating the valid data ready output. If the starting address is not aligned to an 8 double-
word boundary, valid data ready is activated to indicate that the device needs an internal
delay to read the successive words in the array.
M10, M5 and M4 are reserved for future use.
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