256Mb: 3V Embedded Parallel NOR Flash
Power-Up and Reset Characteristics
Power-Up and Reset Characteristics
Table 21: Power-Up Wait Timing Specifications
Note 1 applies to the entire table
Symbol
Parameter
Legacy
tVCH
JEDEC
tVCHEL
tVCQHEL
tVCHWL
tVCQHWL
Min
55
Unit
µs
Notes
2, 3
VCC HIGH to CE# LOW
VCCQ HIGH to CE# LOW
VCC HIGH to WE# LOW
VCCQ HIGH to WE# LOW
–
–
–
55
µs
2, 3
500
500
µs
ns
1. Specifications apply to 60, 70, and 80ns devices unless otherwise noted. The 60ns device
is available upon customer request.
Notes:
2. VCC and VCCQ ramps must be synchronized during power-up.
3. If RST# is not stable for tVCS or tVIOS, the device will not allow any READ or WRITE oper-
ations, and a hardware reset is required.
Figure 27: Power-Up Timing
tVCHEL
VCC
VCCQ
tVCQHEL
CE#
WE#
tVCHWL
tVCQHWL
PDF: 09005aef84bd3b68
m29w_256mb.pdf - Rev. B 5/13 EN
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