256Mb: 3V Embedded Parallel NOR Flash
Bus Operations
Bus Operations
Table 4: Bus Operations
Notes 1 and 2 apply to entire table
8-Bit Mode
16-Bit Mode
DQ15/A-1,
DQ[14:0]
Data output Cell address Data output
A[MAX:0],
DQ15/A-1
Operation CE# OE# WE# RST# VPP/WP#
DQ[14:8]
High-Z
DQ[7:0]
A[MAX:0]
READ
L
L
L
H
L
H
H
X
X3
Cell address
WRITE
H
Command
address
High-Z
Data input4
Command
address
Data input4
STANDBY
H
L
X
H
X
H
H
H
X
X
X
X
High-Z
High-Z
High-Z
High-Z
X
X
High-Z
High-Z
OUTPUT
DISABLE
RESET
X
X
X
L
X
X
High-Z
High-Z
X
High-Z
1. Typical glitches of less than 5ns on CE#, WE#, and RST# are ignored by the device and do
not affect bus operations.
Notes:
2. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW.
3. If WP# is LOW, then the highest or the lowest block remains protected, depending on
line item.
4. Data input is required when issuing a command sequence or when performing data
polling or block protection.
Read
Bus READ operations read from the memory cells, registers, or CFI space. To accelerate
the READ operation, the memory array can be read in page mode where data is inter-
nally read and stored in a page buffer.
Page size is 8 words (16 bytes) and is addressed by address inputs A[2:0] in x16 bus
mode and A[2:0] plus DQ15/A-1 in x8 bus mode. The extended memory blocks and CFI
area do not support page read mode.
A valid READ operation requires setting the appropriate address on the address inputs,
taking CE# and OE# LOW, and holding WE# HIGH. Data I/O signals output the value.
Write
Bus WRITE operations write to the command interface. A valid WRITE operation re-
quires setting the appropriate address on the address inputs. These are latched by the
command interface on the falling edge of CE# or WE#, whichever occurs last. Values on
data I/O signals are latched by the command interface on the rising edge of CE# or
WE#, whichever occurs first. OE# must remain HIGH during the entire operation.
Standby and Automatic Standby
When the device is in read mode, driving CE# HIGH places the device in standby mode
and drives data I/Os to High-Z. Supply current is reduced to standby (ICC2), by holding
CE# within VCC ±0.3V.
During PROGRAM or ERASE operations the device continues to use the program/erase
supply current (ICC3) until the operation completes.
PDF: 09005aef84bd3b68
m29w_256mb.pdf - Rev. B 5/13 EN
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