128Mb 3V Embedded Parallel NOR Flash
Lock Register
2. Block nonvolatile protection bit: when cleared to 1, the block is unprotected; when set
to 0, the block is protected.
3. Block volatile protection bit: when cleared to 1, the block is unprotected; when set to 0,
the block is protected.
Figure 7: Lock Register Program Flowchart
Start
Enter LOCK REGISTER command set
Address/data (unlock) cycle 1
Address/data (unlock) cycle 2
Address/data cycle 3
PROGRAM LOCK REGISTER
Address/data cycle 1
Address/data cycle 2
Polling algorithm
Yes
Done?
No
No
DQ5 = 1
Yes
Success:
Failure:
EXIT PROTECTION command set
(Returns to device read mode)
Address/data cycle 1
READ/RESET
(Returns device to read mode)
Address/data cycle 2
1. Each lock register bit can be programmed only once.
Notes:
2. See the Block Protection Command Definitions table for address-data cycle details.
PDF: 09005aef84daa141
m29w_128mb.pdf - Rev. A 7/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
20
© 2012 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
