128Mb 3V Embedded Parallel NOR Flash
Program Operations
within the targeted block. Then, a fourth bus WRITE cycle sets up the number of words/
bytes to be programmed. Value n is written to the same block address, where n + 1 is the
number of words/bytes to be programmed. Value n + 1 must not exceed the size of the
program buffer, or the operation will abort. A fifth cycle loads the first address and data
to be programmed. Last, n bus WRITE cycles load the address and data for each word/
byte into the program buffer. Addresses must lie within the range from the start address
+1 to the start address + (n - 1).
Optimum programming performance and lower power usage are achieved by aligning
the starting address at the beginning of a 32-word boundary. Any buffer size smaller
than 32 words is allowed within a 32-word boundary, while all addresses used in the op-
eration must lie within the 32-word boundary. In addition, any crossing boundary buf-
fer program will result in a program abort.
To program the content of the program buffer, this command must be followed by a
WRITE TO BUFFER PROGRAM CONFIRM command.
If an address is written several times during a WRITE TO BUFFER PROGRAM operation,
the address/data counter will be decremented at each data load operation, and the data
will be programmed to the last word loaded into the buffer.
Invalid address combinations or the incorrect sequence of bus WRITE cycles will abort
the WRITE TO BUFFER PROGRAM command.
The status register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status
during a WRITE TO BUFFER PROGRAM operation.
The WRITE BUFFER PROGRAM command should not be used to change a bit set to 0
back to 1, and an attempt to do so is masked during the operation. Rather than the
WRITE BUFFER PROGRAM command, the ERASE command should be used to set
memory bits from 0 to 1.
PDF: 09005aef84daa141
m29w_128mb.pdf - Rev. A 7/13 EN
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