256Mb: 3V Embedded Parallel NOR Flash
Memory Organization
Memory Organization
Memory Configuration
The M29DW256G features an asymmetrical block architecture, with 8 parameter and
126 main blocks, divided into four banks providing multiple bank operations. Four pa-
rameter blocks are at the top of the memory address space, and four are at the bottom.
Table 4: Bank architecture
Parameter Blocks
Bank Size Number of Blocks Block Size
Main Blocks
Number of Blocks
Bank
Block Size
128 Kwords
128 Kwords
128 Kwords
128 Kwords
A
B
C
D
32Mb
96Mb
96Mb
32Mb
4
—
—
4
32 Kwords
15
48
48
15
—
—
32 Kwords
Figure 4: Block Addresses
Address lines A23-A0
000000h
007FFFh
800000h
81FFFFh
32 Kwords
128 Kwords
Total of 4
Total of 48
Bank C
parameter
blocks
main blocks
018000h
DE0000h
32 Kwords
128 Kwords
128 Kwords
01FFFFh
Bank A
DFFFFFh
E00000h
020000h
128 Kwords
03FFFFh
E1FFFFh
FC0000h
Total of 15
Total of 15
main blocks
main blocks
1E0000h
128 Kwords
128 Kwords
128 Kwords
32 Kwords
1FFFFFh
200000h
FDFFFFh
FE0000h
Bank D
21FFFFh
FE7FFFh
Total of 48
Total of 4
parameter
blocks
Bank B
main blocks
7E0000h
7FFFFFh
FF8000h
FFFFFFh
128 Kwords
32 Kwords
PDF: 09005aef84ecabef
m29dw_256g.pdf - Rev. A 10/12 EN
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