256Mb: 3V Embedded Parallel NOR Flash
Signal Descriptions
Signal Descriptions
The signal description table below is a comprehensive list of signals for this device fami-
ly. All signals listed may not be supported on this device. See Signal Assignments for in-
formation specific to this device.
Table 3: Signal Descriptions
Name
Type
Description
A[MAX:0]
Input
Address: Selects the cells in the array to access during READ operations. During WRITE oper-
ations, they control the commands sent to the command interface of the program/erase con-
troller.
DQ[15:0]
I/O
Data I/O: Outputs the data stored at the selected address during a READ operation. During
WRITE operations, they represent the commands sent to the command interface of the inter-
nal state machine. During WRITE operations, bits DQ[15:8] are not used. When reading the
status register, these bits should be ignored.
CE#
Input
Chip enable: Activates the device, enabling READ and WRITE operations to be performed.
When CE# is HIGH, the device goes to standby and data outputs are at HIGH-Z.
OE#
WE#
Input
Input
Input
Output enable: Controls the bus READ operation.
Write enable: Controls the bus WRITE operation of the command interface.
VPP/WP#
VPP/Write Protect: Provides two functions. The VPPH function enables the device to bypass
unlock cycles and use an external high voltage power supply to reduce time required for
PROGRAM operations.
Second, When VPP/WP# is LOW, the four outermost blocks of the address space (two 32KW
blocks at the top and two 32KW blocks at the bottom) are protected; PROGRAM and ERASE
operations are ignored and the blocks remain protected regardless of the block protection
status or the RST# pin state. When VPP/WP# is HIGH, the memory reverts to the previous pro-
tection status for those blocks (Refer to Hardware Protection and Bypass Operations for de-
tails).
RST#
Input
Reset: Applies a hardware reset to the device, which is achieved by holding RST# LOW for at
least tPLPX. After RST# goes HIGH, the device is ready for READ and WRITE operations (after
tPHEL or tRHEL, whichever occurs last). See RESET AC Specifications for more details.
RY/BY#
Output Ready busy: Open-drain output that can be used to identify when the device is performing
a PROGRAM or ERASE operation. During PROGRAM or ERASE operations, RY/BY# is LOW,
and is High-Z during read mode, auto select mode, and erase suspend mode. After a hard-
ware reset, READ and WRITE operations cannot begin until RY/BY# goes High-Z (see RESET
AC Specifications for more details).
The use of an open-drain output enables the RY/BY# pins from several devices to be connec-
ted to a single pull-up resistor to VCCQ. A low value will then indicate that one or more of the
devices is busy.
VCC
Supply
Supply voltage: Provides the power supply for READ, PROGRAM, and ERASE operations.
The command interface is disabled when VCC <= VLKO. This prevents WRITE operations from
accidentally damaging the data during power-up, power-down, and power surges. If the pro-
gram/erase controller is programming or erasing during this time, then the operation aborts
and the contents being altered will be invalid.
A 0.1μF capacitor should be connected between VCC and VSS to decouple the current surges
from the power supply. The PCB track widths must be sufficient to carry the currents required
during PROGRAM and ERASE operations (see DC Characteristics).
PDF: 09005aef84ecabef
m29dw_256g.pdf - Rev. A 10/12 EN
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