256Mb: 3V Embedded Parallel NOR Flash
Bus Operations
During PROGRAM or ERASE operations the device will continue to use the program/
erase supply current (ICC3) until the operation completes.
Automatic standby allows the memory to achieve low power consumption during read
mode. After a READ operation, if CMOS levels (VCC ± 0.3 V) are used to drive the bus
and the bus is inactive for tAVQV + 30ns or more, the memory enters automatic standby
where the internal supply current is reduced to the standby supply current, ICC2 (see
DC characteristics). The data inputs/outputs still output data if a READ operation is in
progress. Depending on load circuits connected with data bus, VCCQ, can have a null
consumption when the memory enters automatic standby.
Output Disable
Reset
Data I/Os are High-Z when OE# is HIGH.
During reset mode the device is deselected and the outputs are High-Z. The device is in
reset mode when RST# is LOW. The power consumption is reduced to the standby level,
independently from CE#, OE#, or WE# inputs.
PDF: 09005aef84ecabef
m29dw_256g.pdf - Rev. A 10/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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