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M25PX16 参数 Datasheet PDF下载

M25PX16图片预览
型号: M25PX16
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位,双I / O , 4 KB的界别分组擦除,串行闪存与75 MHz的SPI总线接口 [16-Mbit, dual I/O, 4-Kbyte subsector erase, serial Flash memory with 75 MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 65 页 / 1418 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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M25PX16  
DC and AC parameters  
(1)  
Table 18. AC characteristics (continued)  
Test conditions specified in Table 14 and Table 15  
Symbol  
Alt.  
Parameter  
Min  
Typ(2)  
Max  
Unit  
tCHSH  
tSHCH  
tSHSL  
S active hold time (relative to C)  
5
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
S not active setup time (relative to C)  
tCSH S deselect time  
80  
(4)  
tSHQZ  
tDIS Output Disable time  
8
8
6
Clock Low to Output valid under 30 pF  
tCLQV  
tV  
Clock Low to Output valid under 10 pF  
Output hold time  
tCLQX  
tHLCH  
tCHHH  
tHHCH  
tCHHL  
tHO  
0
5
5
5
5
HOLD setup time (relative to C)  
HOLD hold time (relative to C)  
HOLD setup time (relative to C)  
HOLD hold time (relative to C)  
HOLD to Output Low-Z  
(4)  
tHHQX  
tLZ  
8
8
(4)  
tHLQZ  
tHZ  
HOLD to Output High-Z  
(6)  
tWHSL  
Write Protect setup time  
20  
(6)  
tSHWL  
Write Protect hold time  
100  
Enhanced Program supply voltage High  
(VPPH) to Chip Select Low  
(7)  
tVPPHSL  
200  
ns  
(4)  
tDP  
S High to Deep Power-down mode  
S High to Standby mode  
3
µs  
µs  
(4)  
tRDP  
tW  
30  
15  
Write Status Register cycle time  
Page Program cycle time (256 bytes)  
Page Program cycle time (n bytes)  
Program OTP cycle time (64 bytes)  
Subsector Erase cycle time  
Sector Erase cycle time  
1.3  
ms  
0.8  
ms  
(8)  
tPP  
int(n/8) × 0.025(9)  
5
0.2  
70  
ms  
ms  
s
tSSE  
tSE  
150  
3
0.6  
15  
tBE  
Bulk Erase cycle time  
80  
s
1. 75 MHz operations are allowed only on the VCC range 2.7 V - 3.6 V.  
2. Typical values given for TA = 25° C.  
3. tCH + tCL must be greater than or equal to 1/ fC.  
4. Value guaranteed by characterization, not 100% tested in production.  
5. Expressed as a slew-rate.  
6. Only applicable as a constraint for a WRSR instruction when SRWD is set at ‘1’.  
7. VPPH should be kept at a valid level until the program or erase operation has completed and its result (success or failure) is  
known. Avoid applying VPPH to the W/VPP pin during Bulk Erase.  
8. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are obtained with one  
sequence including all the bytes versus several sequences of only a few bytes (1 n 256).  
9. int(A) corresponds to the upper integer part of A. For example, int(12/8) = 2, int(32/8) = 4 int(15.3) =16.  
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