M25PX16 Serial Flash Embedded Memory
READ STATUS REGISTER
WIP Bit
WEL Bit
The write in progress (WIP) bit indicates whether the memory is busy with a WRITE
STATUS REGISTER cycle, a PROGRAM cycle, or an ERASE cycle. When the WIP bit is set
to 1, a cycle is in progress; when the WIP bit is set to 0, a cycle is not in progress.
The write enable latch (WEL) bit indicates the status of the internal write enable latch.
When the WEL bit is set to 1, the internal write enable latch is set; when the WEL bit is
set to 0, the internal write enable latch is reset and no WRITE STATUS REGISTER, PRO-
GRAM, or ERASE command is accepted.
Block Protect Bits
The block protect bits are non-volatile. They define the size of the area to be software
protected against PROGRAM and ERASE commands. The block protect bits are written
with the WRITE STATUS REGISTER command.
When one or more of the block protect bits is set to 1, the relevant memory area, as de-
fined in the Protected Area Sizes table, becomes protected against PAGE PROGRAM and
SECTOR ERASE commands. The block protect bits can be written provided that the
HARDWARE PROTECTED mode has not been set. The BULK ERASE command is execu-
ted only if all block protect bits are 0.
Top/Bottom Bit
The top/bottom (TB) bit is non-volatile. It can be set and reset with the WRITE STATUS
REGISTER command provided that the WRITE ENABLE command has been issued. The
TB bit is used in conjunction with the block protect bits to determine if the protected
area defined by the block protect bits starts from the top or the bottom of the memory
array:
• When TB is reset to 0 (default value), the area protected by the block protect bits starts
from the top of the memory array
• When TB is set to 1, the area protected by the block protect bits starts from the bot-
tom of the memory array
The TB bit cannot be written when the status register write disable (SRWD) bit is set to 1
and the W# pin is driven LOW. For further information, see on page
SRWD Bit
The status register write disable (SRWD) bit is operated in conjunction with the write
protect (W#/VPP) signal. When the SRWD bit is set to 1 and W#/VPP is driven LOW, the
device is put in the hardware protected mode. In the hardware protected mode, the
non-volatile bits of the status register (SRWD, and the block protect bits) become read-
only bits and the WRITE STATUS REGISTER command is no longer accepted for execu-
tion.
PDF: 09005aef845665a5
m25px16.pdf - Rev. A 11/12 EN
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