欢迎访问ic37.com |
会员登录 免费注册
发布采购

M25P40-VMN6PB 参数 Datasheet PDF下载

M25P40-VMN6PB图片预览
型号: M25P40-VMN6PB
PDF下载: 下载PDF文件 查看货源
内容描述: M25P40 3V的4Mb串行Flash的嵌入式存储器 [M25P40 3V 4Mb Serial Flash Embedded Memory]
分类和应用: 存储内存集成电路光电二极管时钟
文件页数/大小: 54 页 / 717 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号M25P40-VMN6PB的Datasheet PDF文件第20页浏览型号M25P40-VMN6PB的Datasheet PDF文件第21页浏览型号M25P40-VMN6PB的Datasheet PDF文件第22页浏览型号M25P40-VMN6PB的Datasheet PDF文件第23页浏览型号M25P40-VMN6PB的Datasheet PDF文件第25页浏览型号M25P40-VMN6PB的Datasheet PDF文件第26页浏览型号M25P40-VMN6PB的Datasheet PDF文件第27页浏览型号M25P40-VMN6PB的Datasheet PDF文件第28页  
M25P40 Serial Flash Embedded Memory  
WRITE STATUS REGISTER  
Table 7: Status Register Protection Modes  
Memory Content  
W#/VPP  
Signal  
SRWD  
Bit  
Protection  
Mode (PM)  
Status Register  
Write Protection  
Protected  
Area  
Unprotected  
Area  
Notes  
1, 2, 3  
1
0
1
0
0
0
1
1
SOFTWARE  
PROTECTED mode  
(SPM)  
Software protection  
Commands not  
accepted  
Commands  
accepted  
HARDWARE  
PROTECTED mode  
(HPM)  
Hardware protection  
Commands not  
accepted  
Commands  
accepted  
3, 4, 5,  
1. Software protection: status register is writable (SRWD, BP2, BP1, and BP0 bit values can  
be changed) if the WRITE ENABLE command has set the WEL bit.  
Notes:  
2. PAGE PROGRAM, SECTOR ERASE, AND BULK ERASE commands are not accepted.  
3. PAGE PROGRAM and SECTOR ERASE commands can be accepted.  
4. Hardware protection: status register is not writable (SRWD, BP2, BP1, and BP0 bit values  
cannot be changed).  
5. PAGE PROGRAM, SECTOR ERASE, AND BULK ERASE commands are not accepted.  
When the SRWD bit of the status register is 0 (its initial delivery state), it is possible to  
write to the status register provided that the WEL bit has been set previously by a WRITE  
ENABLE command, regardless of whether the W#/VPP signal is driven HIGH or LOW.  
When the status register SRWD bit is set to 1, two cases need to be considered depend-  
ing on the state of the W#/VPP signal:  
• If the W#/VPP signal is driven HIGH, it is possible to write to the status register provi-  
ded that the WEL bit has been set previously by a WRITE ENABLE command.  
• If the W#/VPP signal is driven LOW, it is not possible to write to the status register even  
if the WEL bit has been set previously by a WRITE ENABLE command. Therefore, at-  
tempts to write to the status register are rejected, and are not accepted for execution.  
The result is that all the data bytes in the memory area that have been put in SPM by  
the status register block protect bits (BP2, BP1, BP0) are also hardware protected  
against data modification.  
Regardless of the order of the two events, the HPM can be entered in either of the fol-  
lowing ways:  
• Setting the status register SRWD bit after driving the W#/VPP signal LOW  
• Driving the W#/VPP signal LOW after setting the status register SRWD bit.  
The only way to exit the HPM is to pull the W#/VPP signal HIGH. If the W#/VPP signal is  
permanently tied HIGH, the HPM can never be activated. In this case, only the SPM is  
available, using the status register block protect bits (BP2, BP1, BP0).  
PDF: 09005aef8456654f  
m25p40.pdf - Rev. G 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
24  
© 2011 Micron Technology, Inc. All rights reserved.